SN8F5708 datasheet(42/204 Pages) SONIX

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SN8F5708 Series

Reset and Power-on Controller

Datasheet Rev. 2.4

7.5 External Reset Pin

Programmable external reset pin is configurable in options file. Once it is enabled, it monitors its

shared pin’s logic level. A logical low (lower than 30% of VDD) would immediately trigger system

reset until the input is recovered to high (lager than 70% of VDD).

An optional de-bounce period can improve reset signal’s stability. Instead of immediate reset, the

system reset requires an 8-ms-long logic low to avoid bouncing from a button key. Any signal lower

than de-bounce period would not affect the CPU’s execution.

MCU

VDD

VSS

VCC

GND

RST

47K ohm

0.1uF

100 ohm

MCU

VDD

VSS

VCC

GND

RST

47K ohm

0.1uF

DIODE

100 ohm



Note:

1. The reset circuit is no any protection against unusual power or brown out reset on the

left side of the figure.

2. The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is

necessary to limit any current flowing into reset pin from external capacitor C in

the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical

Over-stress (EOS) on the right side of the figure.

7.6 Software Reset

A software reset would be generated after consecutively set SRSTREQ register. As a result, this

procedure enables firmware’s ability to reset microcontroller (e.g. reset after firmware update).

The following sample C code repeatedly set the least bit of SRST register to perform software reset.

SRST = 0x01;

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