SN8F5708 datasheet(75/204 Pages) SONIX

75 / 204 page

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SN8F5708 Series

GPIO

Datasheet Rev. 2.4

P0: 0x80, P1: 0x90, P2: 0xA0, P3: 0xFC, P4: 0xE8, P5: 0xF8

Bit

Field

Type

Initial

Description

P07

R/W

Read: P0.7 pin’s logic level

Write 1/0: Output logic high or low (applied if P07M = 1)

P06

R/W

Read: P0.6 pin’s logic level

Write 1/0: Output logic high or low (applied if P06M = 1)

P05

R/W

Read: P0.5 pin’s logic level

Write 1/0: Output logic high or low (applied if P05M = 1)

4..0

et cetera

12.3

On-chip Pull-up Resisters

The P0UR to P5UR registers are mapped to each pins’ internal 100 kΩ (in typical value) pull-up

resister.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P0UR

P07UR

P06UR

P05UR

P04UR

P03UR

P02UR

P01UR

P00UR

P1UR

P17UR

P16UR

P15UR

P14UR

P13UR

P12UR

P11UR

P10UR

P2UR

P27UR

P26UR

P25UR

P24UR

P23UR

P22UR

P21UR

P20UR

P3UR

P37UR

P36UR

P35UR

P34UR

P33UR

P32UR

P31UR

P30UR

P4UR

P47UR

P46UR

P45UR

P44UR

P43UR

P42UR

P41UR

P40UR

P5UR

P55UR

P54UR

P53UR

P52UR

P51UR

P50UR

P0UR: 0xF1, P1UR: 0xF2, P2UR: 0xF3, P3UR: 0xF4, P4UR: 0xF5, P5UR: 0xF6

Bit

Field

Type

Initial

Description

P07UR

R/W

On-chip pull-up resister control of P0.7

0: Disable

1: Enable

P06UR

R/W

On-chip pull-up resister control of P0.6

0: Disable

1: Enable

P05UR

R/W

On-chip pull-up resister control of P0.5

0: Disable

1: Enable

4..0

et cetera

* Recommended disable pull-up resister if the pin is output mode or analog function

SN8F5708 Datasheet(PDF) 75 Page - SONiX Technology Company

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