SN8F5708 datasheet(91/204 Pages) SONIX

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SN8F5708 Series

Timer 2

Datasheet Rev. 2.4

15.3

Comparison Output (PWM)

Timer 2 has up to four set of comparison output. Each set (CRC/CC1/CC2/CC3) independently

compares its value to Timer 2 counter (TH2/TL2) and outputs the comparison result on T2COM0 to

T2COM3 pins (shared with P1.0 to P1.3). The comparison result has two output methods: directly

output and indirectly output.

The directly method is that the mapped pin outputs low status if Timer 2 counter is lower than

CRC/CC1/CC2/CC3 register, whereas it outputs high status if Timer 2 counter is equal/lager than

CRC/CC1/CC2/CC3 register. Thus, the output status is changed twice at crossover points. As

CRC/CC1/CC2/CC3 register is equal to Timer 2 counter, a TF2C0/TF2C1/TF2C2/TF2C3 flag is issued

which

can

read/write

firmware.

Compare

interrupt

function

controlled

ET2C0/ET2C1/ET2C2/ET2C3.

16-bit Counter/Timer

TH2/TL2

T2FCx

Timer 2 clock

16-bit

Comparator

Compare module

CCHx/CCLx

TF2

COM

Port

T2COMx

SET

CLR

TH2/TL2

CCHx/CCLx

Reload Value

T2COMx

output

TF2Cx

TF2

TH2/TL2 = CCHx/CCLx.

T2COMx exchanges to high status.

T2 overflows from 0xFFFF to 0x0000.

T2COMx exchanges to low status.

By contrast, the indirectly output method is an event which keep the mapped pin’s previous output

setting until Timer 2 counter overtakes CRC/CC1/CC2/CC3 register value. In this mode, the

transition of the output signal can be configured by software. In other word, the P1.0 register bit

would be affect T2COM0/P1.0 pin when TH2/TL2 equal to CRC registers. A Timer 2 overflow causes

no output change.

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