SN8F5708 datasheet(25/204 Pages) SONIX

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SN8F5708 Series

CPU

Datasheet Rev. 2.4

reset, reset pin reset, watchdog reset, LVD reset…).



0x0001~0x0002: General purpose area to process system reset operation.



0x0003~0x00EB: Multi interrupt vector area. Each of interrupt events has a unique interrupt

vector.



0x00EC~0x3FDF: General purpose area for user program and ISP (EEPROM function).



0x3FE0~0x3FF5: General purpose area for user program. Do not execute ISP.



0x3FF6~0x3FFF: Reserved area. Do not execute ISP.

5.5 Program Memory Security

The SN8F5708 provides security options at the disposal of the designer to prevent unauthorized

access to information stored in FLASH memory. When enable security option, the ROM code is

secured and not dumped complete ROM contents. ROM security rule is all address ROM data

protected and outputs 0x00.

5.6 Data Pointer

A data pointer helps to specify the XRAM and IROM address while performing MOVX and MOVC

instructions. The microcontroller has two set of data pointer (DPH/DPL and DPH1/DPL1) which is

selectable by DPS register. The DPC register controls two functions: next DPTR selection and

automatically increase/decrease DPTR function.

The next DPTR selection can specify which DPTR is anticipated to use after perform MOVX @DPTR

instruction. In other word, the DPS can automatically swap between the two data pointers. To

enable this function: write 0 to DPSEL and fill 1 to NDPS firstly, then write 1 to DPSEL and fill 0 to

NDPS register.

The automatically increase/decrease DPTR function can make an increment or decrement after

perform MOVX @DPTR instruction. As a result, it enables a continuous external RAM access

without re-specified DPTR value. Those functions are controlled by the DPC Register, where there

are separate DPC register bits for each DPTR, to provide high flexibility in data transfers. The DPC

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