SN8F5708 datasheet(69/204 Pages) SONIX

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SN8F5708 Series

MDU

Datasheet Rev. 2.4

11 MDU

The multiplication division unit is an on-chip arithmetic co-processor which enables the

microcontroller to perform additional extended arithmetic operations. This unit provides 32-bit

unsigned division, 16-bit unsigned multiplication, shift and normalize operations. These operations

are identified by the different sequences of writing MD0 to MD5 registers.

11.1

Multiplication (16-bit x 16-bit)

The elements of a multiplication include three parts: multiplicand, multiplier and product. To start

a multiplication requires following writing sequence: MD0 (low byte of multiplicand), MD4 (low

byte of multiplier), MD1 (high byte of multiplicand), and MD5 (high byte of multiplier).

By the end of writing MD5 register, the multiplication is automatically started and takes 11 CPU

cycles for its operation. The product of this term operation would be available to read by a specific

sequence: MD0 (LSB), MD1, MD2, and MD3 (MSB) registers.

11.2

Division (32-bit/16-bit and 16-bit/16-bit)

The MDU supports two kind of division: 32-bit by 16-bit, and 16-bit by 16-bit. The first operation

takes 17 CPU cycles to compute, whereas the second one takes 9 cycles only.

A 32-bit division started by a specific sequence of writing registers: MD0, MD1, MD2, MD3, MD4,

and MD5. In this case, the 32-bit dividend is expected to store in MD3 (most significant bit) to MD0

registers, and 16-bit divisor is stored in MD5 and MD4 registers (MSB in MD5 register).

A 16-bit division operation cooperates with four registers only. The 16-bit dividend is stored in

MD1 and MD0 registers, and the 16-bit divisor is stored in MD5 and MD4 registers (MD1 and MD5

for most signification bit). The appropriate performing sequence is ‘MD0, MD1, MD4, and MD5.’

The MDU starts computing from MD5 register is written. It spends 9 or 17 CPU cycles, depends on

the length of dividend, before the outcome is generated. The quotient is stored in MD3 to MD0

registers for 32-bit division, and MD1 to MD0 registers for 16-bit division (LSB in MD0 register). The

reminder would be placed in MD5 (MSB) and MD4 registers no matter which division is performed.

However, reading MD5 register must be the last operation to indicate the full division is completed.

11.3

Shifting and Normalizing

The shifting and normalizing operations rotate the 32-bit registers (MD3 to MD0, MSB in MD3) for

a certain or uncertain time.

In shift operation, the 32-bit unsigned integer is shifted left or right by a specified number of bits.

The direction and shifting number is specified in ARCON register. A shift operation takes 3 to 18

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