SN8F5708 datasheet(74/204 Pages) SONIX

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SN8F5708 Series

GPIO

Datasheet Rev. 2.4

P1OC Register (0xE4)

Bit

Field

Type

Initial

Description

7..5

R/W

000

Refer to PWM chapter

P06OC

R/W

P0.6 open-drain output mode

0: Disable

1: Enable, output high status becomes to input mode

P05OC

R/W

P0.5 open-drain output mode

0: Disable

1: Enable, output high status becomes to input mode

P13OC

R/W

P1.3 open-drain output mode

0: Disable

1: Enable, output high status becomes to input mode

P12OC

R/W

P1.2 open-drain output mode

0: Disable

1: Enable, output high status becomes to input mode

P11OC

R/W

P1.1 open-drain output mode

0: Disable

1: Enable, output high status becomes to input mode

12.2

Input Data and Output Data

By a read operation from any registers of P0 to P5, the current pin’s logic level would be fetch to

represent its external status. This operation remains functional even the pin is shared with other

function like UART and I2C which can monitor the bus condition in some case.

A write P0 to P5 register value would be latched immediately, yet the value would be outputted

until the mapped P0M – P5M is set to output mode. If the pin is currently in output mode, any

value set to P0 to P5 register would be presented on the pin immediately.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

P07

P06

P05

P04

P03

P02

P01

P00

P17

P16

P15

P14

P13

P12

P11

P10

P27

P26

P25

P24

P23

P22

P21

P20

P37

P36

P35

P34

P33

P32

P31

P30

P47

P46

P45

P44

P43

P42

P41

P40

P55

P54

P53

P52

P51

P50

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