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SN8F5708 Datasheet(PDF) 100 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 100 Page - SONiX Technology Company |
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100 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. PWM Datasheet Rev. 2.4 100 16 PWM The PW1/PW2/PW3 timer respectively includes a 16-bit binary up 2-channel PWM, and one pulse PWM function functions. By the counter reaches the up-boundary value (PW1Y/PW2Y/PW3Y), it clears its counter and triggers an interrupt signal. Each PWM’s duty cycle is controlled by PW1D/PW2D/PW3D register. The PWMs also support one pulse output signal which can disables itself by the end of first PWM cycle. Thus, only one pulse would be generated in this condition. The PWM has two programmable channels shared with GPIO pins and controlled by PWCH[1:0] bit. The output operation must be through enabled each bit/channel of PWCH[1:0] bits. The enabled PWM channel exchanges from GPIO to PWM output. When the PWCH[1:0] bits disables, the PWM channel returns to last status of GPIO mode. The PWM build in IDLE Mode wake-up function if interrupt enable. When PWM timer overflow occurs (counts from PWnY-1 to PWnY), PWMnF would be issued immediately which can read/write by firmware. PWMn interrupt function is controlled by EPWMn. 16-Bit Binary Up Counting Counter PWM Rate PWnEN PWM OUT Clear to 0x0000 PWnPO fosc PWMnF PWnEN Divider ÷1 to ÷128 EN 16-Bit Comparator PWnD Data Buffer Reload PWnDH/PWnDL 16-Bit Comparator PWnY Data Buffer PWMnF Reload PWnYH/PWnYL PWMnF S R Pulse Control M U X M U X GPIO GPIO PWnEN PWCHn0 PWNVn0 PWMn0 PWMn1 Dead Band Control PWNVn1 PWnEN PWCHn1 PWnBH/PWnBL PWnA PWM Time Out 16.1 General PWM PWn timer builds in PWM function controlled by PWnEN and PWCH[1:0] bits. PWMn0, PWMn1 are output pins. The PWMn0, PWMn1 output pins are shared with GPIO pin controlled by PWCH[1:0] bits. When output PWM function, we must be set PWnEN =1. When PWM output signal synchronize finishes, the PWM channel exchanges from GPIO to PWM output. When PWnEN = 0, the PWM channel returns to GPIO mode and last status. PWM signal is generated from the result of PWnY and PWnD comparison combination. When PWnC counts from 0x0000, the PWM outputs high status which is the PWM initial status. PWnC is loaded new data from PWnY register to decide |
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