SN8F5708 datasheet(44/204 Pages) SONIX

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SN8F5708 Series

System Clock and Power Management

Datasheet Rev. 2.4

System Clock and Power Management

For power saving purpose, the microcontroller built in three different operation modes: normal,

IDLE, and STOP mode.

The normal mode means that CPU and peripheral functions are under normally execution. The

system clock is based on the combination of source selection, clock divider, and program memory

wait state. IDLE mode is the situation that temporarily suspends CPU clock and its execution, yet it

remains peripherals’ functionality (e.g. timers, PWM, SPI, UART, and I2C). By contrast, STOP mode

disables all functions and clock generator until a wakeup signal to return normal mode.

8.1 System Clock

The microcontroller includes an on-chip clock generator (IHRC 32MHz), crystal/resonator driver,

and an external clock input. The reset and power-on controller automatically loads clock source

selection during power-on sequence. Therefore, the selected clock source is seen as ‘fosc’ domain

which is a fixed frequency at any time.

Subsequently, the selected clock source (fosc) is divided by 1 to 128 times which is controlled by

CLKSEL register. The CPU input the divided clock as its operation base (named fcpu). Applying

CLKSEL's setting when CLKCMD register be written 0x69.

CKCON = 0x70;

// For change safely the system clock

CLKSEL = 0x05;

// set fcpu = fosc / 4

CLKCMD = 0x69;

// Apply CLKSEL’s setting

CKCON = 0x00;

// IROM fetch = fcpu / 1

fosc

Divider

÷1 to ÷128

IHRC 32MHz

Crystal

External Clock

Clock Source Selection

(set in Options file)

CLKSEL

fcpu

CPU

ROM

interface

CKCON

IROM

ROM interface is built in between CPU and IROM (program memory). It optionally extends the data

fetching cycle in order to support lower speed program memory.

IROM fetching cycle (Instruction cycle) ≦ 8MHz

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