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SN8F5708 Datasheet(PDF) 26 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 26 Page - SONiX Technology Company |
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26 / 204 page  www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. CPU Datasheet Rev. 2.4 26 5.7 Stack Stack can be assigned to any area of internal RAM (IRAM). However, it requires manual assignment to ensure its area does not overlap other RAM’s variables. An overflow and underflow stack could also mistakenly overwrite other RAM’s variables; thus, these factors should be considered while arrange the size of stack. 0x0B 0x0B 0x0B 0x0A PUSH → 0x0A LCALL → 0x0A Address 0x09 POP ← 0x09 RET ← 0x09 0x08 (empty) 0x08 Data 0x08 Data SP = 0x07 SP = 0x08 SP = 0x0A By default, stack pointer (SP register) points to 0x07 which means the stack area begin at IRAM address 0x08. In other word, if a planned stack area is assigned from IRAM address 0xC0, the appropriate SP register is anticipated to set at 0xBF after system reset. An assembly PUSH instruction costs one byte of stack. LCALL, ACALL instructions and interrupt respectively costs two bytes stack. POP-instruction decreases one count, and a RET/RETI subtract two counts of stack pointer. Note: Stack and IRAM share the same area, Keil C51 compiler will not display “error” or “warning” when overlap condition is occurred so user must pay attention. 5.8 Stack and Data Pointer Register Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 DPL DPL7 DPL6 DPL5 DPL4 DPL3 DPL2 DPL1 DPL0 DPH DPH7 DPH6 DPH5 DPH4 DPH3 DPH2 DPH1 DPH0 DPL1 DPL17 DPL16 DPL15 DPL14 DPL13 DPL12 DPL11 DPL10 DPH1 DPH17 DPH16 DPH15 DPH14 DPH13 DPH12 DPH11 DPH10 DPS - - - - - - - DPSEL DPC - - - - NDPS ATMS ATMD ATME |
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