SN8F5708 datasheet(39/204 Pages) SONIX

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SN8F5708 Series

Reset and Power-on Controller

Datasheet Rev. 2.4

7.2 Power-on Sequence

A power-on sequence would be triggered by LVD, watchdog, and external reset pin. It takes place

between the end of reset signal and program execution. Overall, it includes two stages: power

stabilization period, and clock stabilization period.

VDD

VSS

VDD

VSS

Watchdog Normal Run

Watchdog Stop

System Normal Run

System Stop

LVD Detect Level

External Reset

Low Detect

External Reset

High Detect

Watchdog

Overflow

Watchdog

Reset Delay

Time

External

Reset Delay

Time

Power On

Delay Time

Power

External Reset

Watchdog

Reset

System Status

The power stabilization period spends 4.6ms in typical condition. Afterward the microcontroller

fetches CPU Clock Source selection automatically. The selected clock source would be driven, and

the system counts 2048 times of the clock period and 5 times of the internal low-speed oscillator

clocks to ensure its reliability.



Note: In high power noise environment, user can put 10ohm resistor in the front of

0.1uF capacitor & VDD PAD to suppress power noise and avoid IC damage.

SN8F5708 Datasheet(PDF) 39 Page - SONiX Technology Company

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