71M6541DSLASHFSLASHG datasheet(58/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Refer to the 71M6xxx Data Sheet for information on reading the VCC sensor in the 71M6x01 devices.

2.5.7

UART and Optical Interface

The 71M6541D/F/G and 71M6542F/G provide two asynchronous interfaces, UART0 and UART1. Both

can be used to connect to AMR modules, user interfaces, etc., and also support a mechanism for

programming the on-chip flash memory.

Referring to Figure 19, UART1 includes an interface to implement an IR/optical port. The pin OPT_TX is

designed to directly drive an external LED for transmitting data on an optical link. The pin OPT_RX has

the same threshold as the RX pin, but can also be used to sense the input from an external photo detector

used as the receiver for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port

(UART1).

The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV (I/O RAM 0x2456[0])

and OPT_RXINV (I/O RAM 0x2457[1]), respectively. Additionally, the OPT_TX output may be modulated at

38 kHz. Modulation is available in MSN and BRN modes (see Table 67). The OPT_TXMOD bit (I/O RAM

0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O RAM 0x2457[5:4]) ,

which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means that OPT_TX is

low for 6.25% of the period.

When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is

via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The

OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse

modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured

as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).

OPT_TXMOD = 0

OPT_TXMOD = 1,

OPT_FDC = 2 (25%)

1/38kHz

OPT_TXINV

from

OPT_TX UART

MOD

DUTY

OPT_TX

OPT_TXMOD

OPT_FDC

OPT_TXE[1:0]

V3P3

Internal

DIO2

WPULSE

VARPULSE

Figure 18: Optical Interface

Bit Banged Optical UART (Third UART)

As shown in Figure 19, the 71M654x can also be configured to drive the optical UART with a DIO signal

in a bit banged configuration. When control bit OPT_BB (I/O RAM 0x2022[0]) is set, the optical port is

driven by DIO5 and the SEGDIO5 pin is driven by UART1_TX. This configuration is typically used when

the two dedicated UARTs must be connected to high speed clients and a slower optical UART is

permissible.

71M6541D/F/G Datasheet(PDF) 58 Page - Maxim Integrated Products

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