71M6541DSLASHFSLASHG datasheet(84/166 Pages) MAXIM

84 / 166 page

71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

3.2.3

SLP Mode

When the V3P3SYS pin voltage drops below 2.8 VDC, the 71M654x enters BRN mode and the V3P3D

pin obtains power from the VBAT pin instead of the V3P3SYS pin. Once in BRN mode, the MPU may

invoke SLP mode by setting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of SLP mode is to

consume the least amount power while still maintaining the RTC (Real Time Clock), temperature

compensation of the RTC, and the non-volatile portions of the I/O RAM.

In SLP mode, the V3P3D pin is disconnected, removing all sources of current leakage from the VBAT pin.

The non-volatile I/O RAM locations and the SLP mode functions, such as the temperature sensor,

oscillator, RTC, and the RTC temperature compensation are powered by the VBAT_RTC pin. SLP mode

can be exited only by a system power-up event or one of the wake methods described in 3.4 Wake Up

Behavior.

If the SLEEP bit is asserted when V3P3SYS pin power is present (i.e., while in MSN mode), the 71M654x

enters SLP mode, resetting the internal WAKE signal, at which point the 71M654x begins the standard

wake from sleep procedures as described in 3.4 Wake Up Behavior.

When power is restored to the V3P3SYS pin, the 71M654x transitions from SLP mode to MSN mode and

the MPU PC (Program Counter) is initialized to 0x0000. At this point, the XRAM is in an undefined state,

but non-volatile I/O RAM locations are preserved (the shaded locations in Table 76 are non-volatile).

71M6541D/F/G Datasheet(PDF) 84 Page - Maxim Integrated Products