71M6541DSLASHFSLASHG datasheet(71/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Table 60: EECTRL Bits for 2-pin Interface

Status

Bit

Name

Read/

Write

Reset

State

Polarity

Description

ERROR

Positive

1 when an illegal command is received.

BUSY

Positive

1 when serial data bus is busy.

RX_ACK

Positive

1 indicates that the EEPROM sent an ACK bit.

TX_ACK

Positive

1 indicates that an ACK bit has been sent to the

EEPROM.

3:0

CMD[3:0]

0000

Positive

CMD[3:0]

Operation

0000

No-op command.

0010

Receive a byte from the EEPROM

and send ACK.

0011

Transmit a byte to the EEPROM.

0101

Issue a STOP sequence.

0110

Receive the last byte from the

EEPROM and do not send ACK.

1001

Issue a START sequence.

Others

No operation, set the ERROR bit.

The EEPROM interface can also be operated by controlling the DIO2 and DIO3 pins directly. The

direction of the DIO line can be changed from input to output and an output value can be written

with a single write operation, thus avoiding collisions (see Table 15 Port Registers (SEGDIO0-15)).

Therefore, no resistor is required in series SDATA to protect against collisions.

2.5.9.2 Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin

A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is

selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are

shown in Table 61. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM

or read from the EEPROM, depending on the values of the EECTRL bits.

2.5.9.3 Three-Wire (µ-Wire/SPI) EEPROM Interface with Separate Di/DO Pins

If DIO_EEX[1:0]=11, the three-wire interface is the same as above, except DI and DO are separate pins.

In this case, SEGDIO3 becomes DO and SEGDIO8 becomes DI. The timing diagrams are the same as

for DIO_EEX[1:0]=10 except that all output data appears on DO and all input data is expected on DI. In

this mode, DI is ignored while data is being received on DO. This mode is compatible with SPI modes 0,0

and 1,1 where data is shifted out on the falling edge of the clock and is strobed in on the rising edge of

the clock.

Table 61: EECTRL Bits for the 3-Wire Interface

Control

Bit

Name

Read/

Write

Description

WFR

Wait for Ready. If this bit is set, the trailing edge of BUSY is delayed until

a rising edge is seen on the data line. This bit can be used during the

last byte of a Write command to cause the INT5 interrupt to occur when

the EEPROM has finished its internal write sequence. This bit is ignored

if Hi-Z=0.

BUSY

Asserted while the serial data bus is busy. When the BUSY bit falls, an

INT5 interrupt occurs.

HiZ

Indicates that the SD signal is to be floated to high impedance immediately

after the last SDCK rising edge.

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