71M6541DSLASHFSLASHG datasheet(87/166 Pages) MAXIM

87 / 166 page

71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

There is no internal digital state that could deactivate the WDT. For debug purposes, however, the WDT

can be disabled by raising the ICE_E pin to 3.3 VDC.

In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit (I/O RAM

0x28B4[7]). The watchdog timer is also reset when the 71M654x wakes from LCD or SLP mode, and

when ICE_E = 1.

3.4

Wake Up Behavior

As described above, the part always wakes-up in MSN mode when system power is restored. As

described in 3.2 Battery Modes, transitions from both LCD and SLP mode to BRN mode can be initiated

by a wake-up timer timeout, when the pushbutton (PB) input is high, a rising edge on SEGDIO4, or a high

logic level on SEGDIO52 or SEGDIO55, or by activity on the RX or OPT_RX pins.

3.4.1

Wake on Hardware Events

The following pin signal events wake the 71M654x from SLP or LCD mode: a high level on the PB pin, either

edge on the RX pin, a rising edge on the SEGDIO4 pin, a high level on the SEGDIO52 pin (71M6542F/G

only), or a high level on the SEGDIO55 pin or either edge on the OPT_RX pin. See Table 69 for de-bounce

details on each pin and for further details on the OPT_RX/SEGDIO55 pin. The SEGDIO4, SEGDIO52

(71M6542F/G only), and SEGDIO55 pins must be configured as DIO inputs and their wake enable (EW_x

bits) must be set. In SLP and LCD modes, the MPU is held in reset and cannot poll pins or react to

interrupts. When one of the hardware wake events occurs, the internal WAKE signal rises and within

three CK32 cycles the MPU begins to execute. The MPU can determine which one of the pins

awakened it by checking the WF_PB, WF_RX, WF_SEGDIO4, WF_DIO52 (71M6542F/G only), or

WF_DIO55 flags (see Table 69).

If the part is in SLP or LCD mode, it can be awakened by a high level on the PB pin. This pin is normally

pulled to GND and can be connected externally so it may be pulled high by a push button depression.

Some pins are de-bounced to reject EMI noise. Detection hardware ignores all transitions after the initial

transition. Table 69 shows which pins are equipped with de-bounce circuitry.

Pins that do not have de-bounce circuits must still be high for at least 2 µs to be recognized.

The wake enable and flag bits are also shown in Table 69. The wake flag bits are set by hardware when

the MPU wakes from a wake event. Note that the PB flag is set whenever the PB is pushed, even if the

part is already awake.

Table 71 lists the events that clear the WF flags.

In addition to push buttons and timers, the part can also reboot due to the RESET pin, the RESET bit (I/O

RAM 0x2200[3]), the WDT, the cold start detector, and E_RST. As seen in Table 69, each of these

mechanisms has a flag bit to alert the MPU to the source of the wakeup. If the wake-up is caused by

return of system power, there is no active WF flag and the VSTAT[2:0] field (SFR 0xF9[2:0]) indicate that

system power is stable.

71M6541D/F/G Datasheet(PDF) 87 Page - Maxim Integrated Products