71M6541DSLASHFSLASHG datasheet(18/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS

signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally,

MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by

CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:

•

CHOP_E[1:0] (I/O RAM 0x2106[3:2])

•

MUX_DIV[3:0] (I/O RAM 0x2100[7:4])

•

FIR_LEN[1:0] (I/O RAM 0x210C[2:1])

•

ADC_DIV (I/O RAM 0x2200[5])

The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as

determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the

rising edge of CK32, the 32-kHz clock.

It is required that MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) be set to zero while changing the ADC

configuration to minimize system transients. After all configuration bits are set, MUX_DIV[3:0]

should be set to the required value.

Additionally, the ADC can be configured to operate at one-half rate (32768*75=2.46MHz). In this mode,

the bias current to the ADC amplifiers is reduced and overall system power is reduced. The ADC_DIV

(I/O RAM 0x2200[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] is set to 01 (288),

each conversion requires 4 XTAL cycles, resulting in a 2520Hz sample rate when MUX_DIV[3:0] = 3.

Note that in order to work with these power-reducing settings, a corresponding CE code is required.

The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:

Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1)

Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)

The duration of a multiplexer frame in CK32 cycles is:

MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]

The duration of a multiplexer frame in CK_FIR cycles is:

MUX frame duration (CK_FIR cycles) =

[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)

The ADC conversion sequence is programmable through the MUXx_SEL control fields (I/O RAM 0x2100

to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F/G and four ADC time

slots in the 71M6542F/G, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression

MUXx_SEL[3:0] = n, ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input

number or ADC handle (i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid

ADC handles in the 71M654x devices. For example, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the

sample from the IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during

time slot 0. See Table 1 and Table 2 for the appropriate MUXx_SEL[3:0] settings and other settings

applicable to a particular CE code.

Note that when the remote sensor interface is enabled, and even though the samples corresponding to

the remote sensor current (IBP-IBN) do not pass through the multiplexer, the MUX2_SEL[3:0] and

MUX3_SEL[3:0] control fields must be written with a valid ADC handle that is not being used. Typically,

ADC1 is used for this purpose (see Table 2). In this manner, the ADC1 handle, which is not used in the

71M6541D/F/G or 71M6542F/G, is used as a place holder in the multiplexer frame, in order to generate

the correct multiplexer frame sequence and the correct sample rate. The resulting sample data stored

in CE RAM 0x1 is undefined and is ignored by the CE code. Meanwhile, the digital isolation interface

takes care of automatically storing the samples for the remote interface current (IBP-IBN) in CE RAM

0x2.

71M6541D/F/G Datasheet(PDF) 18 Page - Maxim Integrated Products

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