71M6541DSLASHFSLASHG datasheet(25/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time

slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.

The MPU reads and writes the XRAM shared between the CE and MPU as the primary means of data

communication between the two processors.

Table 3 shows the CE addresses in XRAM allocated to analog inputs from the AFE.

The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and

accumulators. This hardware is controlled through the I/O RAM control field EQU[2:0], equation assist

(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW, pulse count assist (I/O RAM

0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).

SUM_SAMPS[12:0] supports an accumulation scheme where the incremental energy values from up to

SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation interval. The integration time

for each energy output is, for example, SUM_SAMPS[12:0]/2520.6 (with MUX_DIV[3:0] = 011, I/O RAM

0x2100[7:4] and FIR_LEN[1:0] = 10, I/O RAM 0x210C[2:1]). CE hardware issues the XFER_BUSY interrupt

when the accumulation is complete.

2.3.3

CE Communication with the MPU

The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY, XPULSE, YPULSE, WPULSE and

VPULSE. These are connected to the MPU interrupt service. CE_BUSY indicates that the CE is actively

processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is

updating to the output region of the CE RAM, which occurs whenever an accumulation cycle has been

completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.

XPULSE, YPULSE, VPULSE, and WPULSE can be configured to interrupt the MPU and indicate zero

crossings of the mains voltage, sag failures, or other significant events. Additionally, these signals can be

connected directly to DIO pins to provide direct outputs for the CE. Interrupts associated with these

signals always occur on the leading edge (see “External” interrupt source No. 2 in Figure 16).

2.3.4

Meter Equations

The 71M6541D/F/G and 71M6542F/G provide hardware assistance to the CE in order to support various

meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The

Compute Engine (CE) firmware for industrial configurations can implement the equations listed in Table 8.

EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of

phases used for metering.

Table 8: Inputs Selected in Multiplexer Cycles

EQU

Description

Wh and VARh formula

Recommended

Multiplexer

Sequence

Element 0

Element 1

Element 2

1-element, 2-W, 1

f with

neutral current sense

VA · IA

VA · IB

N/A

IA VA IB

1-element, 3-W, 1

VA(IA-IB)/2

N/A

IA VA IB

2 †

2-element, 3-W, 3

f Delta

VA · IA

VB · IB

N/A

IA VA IB VB

Note:

Optionally, IB may be used to measure neutral current

† 71M6542F/G only

2.3.5

Real-Time Monitor (RTM)

The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable

XRAM locations at full sample rate. The four monitored locations, as selected by the I/O RAM registers

RTM0[9:8], RTM0[7:0], RTM1[9:8], RTM1[7:0], RTM2[9:8], RTM2[7:0], RTM3[9:8], and RTM3[7:0], are

serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code

pass. The RTM can be enabled and disabled with control bit RTM_E (I/O RAM 0x2106[1]). The RTM

output is clocked by CKTEST. Each RTM word is clocked out in 35 CKCE cycles (1 CKCE cycle is

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