71M6541DSLASHFSLASHG datasheet(76/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Table 64: SPI Registers

Name

Location

Rst

Dir

Description

EX_SPI

2701[7]

R/W

SPI interrupt enable bit.

SPI_CMD

SFR FD[7:0]

–

SPI command. The 8-bit command from the bus master.

SPI_E

270C[4]

R/W

SPI port enable bit. It enables the SPI interface on pins

SEGDIO36 – SEGDIO39.

IE_SPI

SFR F8[7]

R/W

SPI interrupt flag. Set by hardware, cleared by writing a 0.

SPI_SAFE

270C[3]

R/W

Limits SPI writes to SPI_CMD and a 16 byte region in

DRAM when set. No other write operations are permitted.

SPI_STAT

2708[7:0]

SPI_STAT contains the status results from the previous

SPI transaction.

Bit 7: Ready error: The 71M654x was not ready to read

or write as directed by the previous command.

Bit 6: Read data parity: This bit is the parity of all bytes

read from the 71M654x in the previous command. Does

not include the SPI_STAT byte.

Bit 5: Write data parity: This bit is the overall parity of the

bytes written to the 71M654x in the previous command.

It includes CMD and ADDR bytes.

Bit 4-2: Bottom 3 bits of the byte count. Does not include

ADDR and CMD bytes. One, two, and three byte

instructions return 111.

Bit 1: SPI FLASH mode: This bit is zero when the TEST

pin is zero.

Bit 0: SPI FLASH mode ready: Used in SPI FLASH

mode. Indicates that the flash is ready to receive

another write instruction.

71M6541D/F/G Datasheet(PDF) 76 Page - Maxim Integrated Products

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