71M6541DSLASHFSLASHG datasheet(33/166 Pages) MAXIM

33 / 166 page

71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions

faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save

and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.

By selecting the R80515 core in the Keil compiler project settings and by using the compiler directive

“MODC2”, dual data pointers are enabled in certain library routines.

An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred

to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction

MOVX A,@Ri or MOVX @Ri,A.

Internal Data Memory Map and Access

The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory

address is always 1 byte wide. Table 11 shows the internal data memory map.

The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory

is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of

Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32

bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW, SFR

0xD0 ) select which bank is in use. The next 16 bytes form a block of bit addressable memory space at

addresses 0x00-0x7F. All the bytes in the lower 128 bytes are accessible through direct or indirect

addressing.

Table 11: Internal Data Memory Map

Address Range

Direct Addressing

Indirect Addressing

0x80

0xFF

Special Function Registers (SFRs)

RAM

0x30

0x7F

Byte addressable area

0x20

0x2F

Bit addressable area

0x00

0x1F

2.4.2

Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 12.

Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read

access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs

specific to the 71M654x are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x90,

etc., are bit addressable, all others are byte addressable.

Table 12: Special Function Register Map

Hex/

Bin

Bit

Addressable

Byte Addressable

Bin/

Hex

X000

X001

X010

X011

X100

X101

X110

X111

FLAG1

STAT

REMOTE0

SPI1

IFLAGS

WDCON

PSW

T2CON

IRCON

IEN1

IP1

S0RELH

S1RELH

PDATA

P3 (DIO12:15)

FLSHCTL

FL_BANK PGADR

IEN0

IP0

S0RELL

P2 (DIO8:11)

71M6541D/F/G Datasheet(PDF) 33 Page - Maxim Integrated Products

71M6541D/F/G Datasheet(HTML) 33 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL