71M6541DSLASHFSLASHG datasheet(73/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Figure 25: 3-Wire Interface. Write Command when CNT=0

Figure 26: 3-Wire Interface. Write Command when HiZ=1 and WFR=1.

2.5.10 SPI Slave Port

The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM

and I/O RAM locations. It is also able to send commands to the MPU. The interface to the slave port

consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed with the

combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39.

Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash

programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The

SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).

Possible applications for the SPI interface are:

1) An external host reads data from CE locations to obtain metering information. This can be used in

applications where the 71M654x function as a smart front-end with preprocessing capability. Since

the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but

not SFRs or the 80515-internal register bank.

2) A communication link can be established via the SPI interface: By writing into MPU memory locations,

the external host can initiate and control processes in the 71M654x MPU. Writing to a CE or MPU

location normally generates an interrupt, a function that can be used to signal to the MPU that the

byte that had just been written by the external host must be read and processed. Data can also be

inserted by the external host without generating an interrupt.

3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the

71M654x as an analog front-end (AFE).

4) Flash programming by the external host (SPI Flash Mode).

SPI Transactions

A typical SPI transaction is as follows. While SPI_CSZ is high, the port is held in an initialized/reset state.

During this state, SPI_DO is held in Hi-Z state and all transitions on SPI_CLK and SPI_DI are ignored.

When SPI_CSZ falls, the port begins the transaction on the first rising edge of SPI_CLK. As shown in

Table 62, a transaction consists of an optional 16 bit address, an 8 bit command, an 8 bit status byte,

followed by one or more bytes of data. The transaction ends when SPI_CSZ is raised. Some transactions

may consist of a command only.

CNT Cycles (0 shown)

Write -- No HiZ

INT5 not issued

CNT Cycles (0 shown)

Write -- HiZ

INT5 not issued

EECTRL Byte Written

SCLK (output)

BUSY (bit)

SDATA (output)

SCLK (output)

BUSY (bit)

SDATA (output)

(HiZ)

SDATA output Z

(LoZ)

CNT Cycles (6 shown)

Write -- With HiZ and WFR

EECTRL Byte Written

SCLK (output)

BUSY

(bit)

SDATA (out/in)

BUSY

READY

(From EEPROM)

INT5

(From 654x)

SDATA output Z

(HiZ)

(LoZ)

71M6541D/F/G Datasheet(PDF) 73 Page - Maxim Integrated Products

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