71M6541DSLASHFSLASHG datasheet(37/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

2.4.4

Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set

and of the associated op-codes is contained in the 71M654X Software User’s Guide (SUG).

2.4.5

UARTs

The 71M6541D/F/G and 71M6542F/G include a UART (UART0) that can be programmed to

communicate with a variety of AMR modules and other external devices. A second UART (UART1) is

connected to the optical port, as described in 2.5.7 UART and Optical Interface.

The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor

at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as

follows:

•

UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are

input LSB first.

•

UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.

Several UART-related registers are available for the control and buffering of serial data.

A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0

and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and

when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the

transmission by the associated UART. Received data are available by reading from the receive buffer.

Both UARTs can simultaneously transmit and receive data.

WDCON[7] (SFR 0xD8) selects whether timer 1 or the internal baud rate generator is used. All UART

transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for

variable communication baud rates from 300 to 38400 bps. Table 17 shows how the baud rates are

calculated. Table 18 shows the selectable UART operation modes.

Table 17: Baud Rate Generation

Using Timer 1

(WDCON[7] = 0)

Using Internal Baud Rate Generator

(WDCON[7] = 1)

UART0

smod * f

CKMPU/ (384 * (256-TH1))

smod * f

CKMPU/(64 * (2

10-S0REL))

UART1

N/A

fCKMPU/(32 * (2

10-S1REL))

S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers.

(S0RELL, S0RELH, S1RELL, S1RELH are SFR 0xAA, SFR 0xBA, SFR 0x9D and SFR 0xBB, respectively) SMOD

is the SMOD bit in the SFR PCON register (SFR 0x87). TH1(SFR 0x8D) is the high byte of timer 1.

Table 18: UART Modes

UART 0

UART 1

Mode 0

N/A

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator)

Mode 1

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

or timer 1)

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator)

Mode 2

Start bit, 8 data bits, parity, stop bit,

fixed baud rate 1/32 or 1/64 of fCKMPU

N/A

Mode 3

Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud rate

generator or timer 1)

N/A

Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of

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