71M6541DSLASHFSLASHG datasheet(19/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],

MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.

Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6541D/F/G and

71M6542F/G.

Table 4 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC.

All listed registers are 0 after reset and wake from battery modes, and are readable and writable.

Table 4: Multiplexer and ADC Configuration Bits

Name

Location

Description

MUX0_SEL[3:0]

2105[3:0]

Selects the ADC input converted during time slot 0.

MUX1_SEL[3:0]

2105[7:4]

Selects the ADC input converted during time slot 1.

MUX2_SEL[3:0]

2104[3:0]

Selects the ADC input converted during time slot 2.

MUX3_SEL[3:0]

2104[7:4]

Selects the ADC input converted during time slot 3.

MUX4_SEL[3:0]

2103[3:0]

Selects the ADC input converted during time slot 4.

MUX5_SEL[3:0]

2103[7:4]

Selects the ADC input converted during time slot 5.

MUX6_SEL[3:0]

2102[3:0]

Selects the ADC input converted during time slot 6.

MUX7_SEL[3:0]

2102[7:0]

Selects the ADC input converted during time slot 7.

MUX8_SEL[3:0]

2101[3:0]

Selects the ADC input converted during time slot 8.

MUX9_SEL[3:0]

2101[7:0]

Selects the ADC input converted during time slot 9.

MUX10_SEL[3:0]

2100[3:0]

Selects the ADC input converted during time slot 10.

ADC_DIV

2200[5]

Controls the rate of the ADC and FIR clocks.

MUX_DIV[3:0]

2100[7:4]

The number of ADC time slots in each multiplexer frame (maximum = 11).

PLL_FAST

2200[4]

Controls the speed of the PLL and MCK.

FIR_LEN[1:0]

210C[1]

Determines the number of ADC cycles in the ADC decimation FIR filter.

DIFFA_E

210C[4]

Enables the differential configuration for analog input pins IAP-IAN.

DIFFB_E

210C[5]

Enables the differential configuration for analog input pins IBP-IBN.

RMT_E

2709[3]

Enables the remote sensor interface transforming pins IBP-IBN into a

digital balanced differential pair for communications with the 71M6x01

sensor.

PRE_E

2704[5]

Enables the 8x pre-amplifier.

Refer to Table 76 starting on page 111 for more complete details about these I/O RAM locations.

2.2.3

Delay Compensation

When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that

phase must be sampled at the same instant. Otherwise, the phase difference,

Ф, introduces errors.

delay

360

⋅

Where f is the frequency of the input signal, T = 1/f and tdelay is the sampling delay between current and

voltage.

Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the

other one for current) controlled to sample simultaneously. Maxim’s Single-Converter Technology,

however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass

filters. The all-pass filter corrects for the conversion time difference between the voltage and the

corresponding current samples that are obtained with a single multiplexed A/D converter.

The “constant delay” all-pass filter provides a broad-band delay 360

o –

θ, which is precisely matched to

the difference in sample time between the voltage and the current of a given phase. This digital filter

does not affect the amplitude of the signal, but provides a precisely controlled phase response.

The recommended ADC multiplexer sequence samples the current first, immediately followed by

sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle

Ф relative to

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