71M6541DSLASHFSLASHG datasheet(38/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant

1. 8-bit serial modes with parity can be simulated by setting and reading the 9

th bit, using the

control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)

registers for transmit and RB81 bit in S1CON[2] for receive operations.

The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals

for inter-processor communication in multi-processor systems. In this case, the slave processors have bit

SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs

the slave’s address, it sets the 9

th bit to 1, causing a serial port receive interrupt in all the slaves. The

slave processors compare the received byte with their address. If there is a match, the addressed slave

clears SM20 or SM21 and receive the rest of the message. The rest of the slave’s ignores the

message. After addressing the slave, the host outputs the rest of the message with the 9

th bit set to 0, so

no additional serial port receive interrupts are generated.

UART Control Registers:

The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON

and S1CON shown in Table 19 and Table 20, respectively, and the PCON register shown in Table 21.

Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice

would be to clear them with a bit operation, but this must be avoided. The hardware implements

bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after

the read, but before the write, its flag is cleared unintentionally.

The proper way to clear these flag bits is to write a byte mask consisting of all ones except for

a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

Table 19: The S0CON (UART0) Register (SFR 0x98)

Bit

Symbol

Function

S0CON[7]

SM0

The SM0 and SM1 bits set the UART0 mode:

Mode

Description

SM0

SM1

N/A

8-bit UART

9-bit UART

S0CON[6]

SM1

S0CON[5]

SM20

Enables the inter-processor communication feature.

S0CON[4]

REN0

If set, enables serial reception. Cleared by software to disable reception.

S0CON[3]

TB80

The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the

MPU, depending on the function it performs (parity check, multiprocessor

communication etc.)

S0CON[2]

RB80

In Modes 2 and 3 it is the 9

th data bit received. In Mode 1, SM20 is 0,

RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by

software.

S0CON[1]

TI0

Transmit interrupt flag; set by hardware after completion of a serial transfer.

Must be cleared by software (see Caution above).

S0CON[0]

RI0

Receive interrupt flag; set by hardware after completion of a serial reception.

Must be cleared by software (see Caution above).

71M6541D/F/G Datasheet(PDF) 38 Page - Maxim Integrated Products

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