71M6541DSLASHFSLASHG datasheet(20/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

the current. The delay compensation implemented in the CE aligns the voltage samples with their

corresponding current samples by first delaying the current samples by one full sample interval (i.e.,

360

o), then routing the voltage samples through the all-pass filter, thus delaying the voltage samples by

360

o -

θ, resulting in the residual phase error between the current and its corresponding voltage of θ – Ф.

The residual phase error is negligible, and is typically less than ±1.5 milli-degrees at 100Hz, thus it does

not contribute to errors in the energy measurements.

When using remote sensors, the CE performs the same delay compensation described above to align

each voltage sample with its corresponding current sample. Even though the remote current samples do

not pass through the 71M654x multiplexer, their timing relationship to their corresponding voltages is

fixed and precisely known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as

shown in Table 1 and Table 2.

2.2.4

ADC Pre-Amplifier

The ADC pre-amplifier is a low-noise differential amplifier with a fixed gain of 8 available only on the IAP-

IAN sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled,

the supply current of the pre-amplifier is <10 nA and the gain is unity. With proper settings of the PRE_E

and DIFFA_E (I/O RAM 0x210C[4]) bits, the pre-amplifier can be used whether differential mode is

selected or not. For best performance, the differential mode is recommended. In order to save power, the

bias current of the pre-amplifier and ADC is adjusted according to the ADC_DIV control bit (I/O RAM

0x2200[5]).

2.2.5

A/D Converter (ADC)

A single 2

nd order delta-sigma A/D converter digitizes the voltage and current inputs to the device. The

resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 1, I/O RAM 0x210C[2:1]), or 22 bits

(FIR_LEN[1:0] = 2). The ADC is clocked by CKADC.

Initiation of each ADC conversion is controlled by MUX_CTRL internal circuit as described above. At the

end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by

the multiplexer selection. FIR data is stored LSB justified, but shifted left 9 bits.

2.2.6

FIR Filter

The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.

The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each

ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer

selection as shown in Table 1 and Table 2.

2.2.7

Voltage References

A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper

stabilized, i.e., the chopper circuit can be enabled or disabled by the MPU using the I/O RAM control field

CHOP_E[1:0] (I/O RAM 0x2106[3:2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the

chopper circuit in regular or inverted operation, or in toggling modes (recommended). When the

chopper circuit is toggled in between multiplexer cycles, dc offsets on VREF are automatically be

averaged out, therefore the chopper circuit should always be configured for one of the toggling modes.

Since the VREF band-gap amplifier is chopper-stabilized, the dc offset voltage, which is the most

significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the

chopper circuit. Both the 71M654x and the 71M6x01 feature chopper circuits for their respective VREF

voltage reference.

The general topology of a chopped amplifier is shown in Figure 8. The CROSS signal is an internal on-

chip signal and is not accessible on any pin or register.

71M6541D/F/G Datasheet(PDF) 20 Page - Maxim Integrated Products

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