71M6541DSLASHFSLASHG datasheet(36/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

Port Registers:

SEGDIO0 through SEGDIO15 are controlled by Special Function Registers P0, P1, P2 and P3 as shown in

Table 15. Above SEGDIO15, the LCD_SEGDIOn[ ] registers in I/O RAM are used. Since the direction bits

are contained in the upper nibble of each SFR Pn register and the DIO bits are contained in the lower nibble,

it is possible to configure the direction of a given DIO pin and set its output value with a single write operation,

thus facilitating the implementation of bit-banged interfaces. Writing a 1 to a DIO_DIR bit configures the

corresponding DIO as an output, while writing a 0 configures it as an input. Writing a 1 to a DIO bit causes

the corresponding pin to be at high level (V3P3), while writing a 0 causes the corresponding pin to be held

at a low level (GND). See 2.5.8 Digital I/O for additional details.

Table 15: Port Registers (SEGDIO0-15)

SFR

Name

SFR

Address

0x80

DIO_DIR[3:0]

DIO[3:0]

0x90

DIO_DIR[7:4]

DIO[7:4]

0xA0

DIO_DIR[11:8]

DIO[11:8]

0xB0

DIO_DIR[15:12]

DIO[15:11]

Ports P0-P3 on the chip are bi-directional and control SEGDIO0-15. Each port consists of a Latch (SFR

P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of

these ports. Even if a DIO pin is configured as an output, the state of the pin can still be read by the

MPU, for example when counting pulses issued via DIO pins that are under CE control.

At power-up SEGDIO0-15 are configured as outputs, but the pins are in a high-impedance state

because PORT_E=0 (I/O RAM 0x270C[5]). Host firmware should first configure SEGDIO0-15 to the

desired state, then set PORT_E=1 to enable the function.

Clock Stretching (CKCON)

The three low order bits of the CKCON[2:0] (SFR 0x8E) register define the stretch memory cycles that

are used for MOVX instructions when accessing external peripherals. The practical value of this register

for the 71M6541D/F/G and 71M6542F/G is to guarantee access to XRAM between CE, MPU, and SPI.

Table 16 shows how the signals of the External Memory Interface change when stretch values are set

from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the

CKCON[2:0] (001), which is shown in bold in the table, performs the MOVX instructions with a stretch

value equal to 1.

Table 16: Stretch Memory Cycle Width

CKCON[2:0]

Stretch

Value

Read Signal Width

Write Signal Width

memaddr

memrd

memaddr

memwr

000

001

010

011

100

101

110

111

71M6541D/F/G Datasheet(PDF) 36 Page - Maxim Integrated Products

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