R5F3640MNFB datasheet(33/398 Pages) RENESAS

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REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 12 of 373

M16C/64 Group

1. Overview

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

NOTES:

Consult the oscillator manufacturer regarding the oscillation characteristics.

TXD2, SDA2, and SCL2 are N-channel open-drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be

selected as CMOS output pins or N-channel open-drain output pins by a program.

Table 1.7

Pin Functions (2)

Signal Name

Pin Name

I/O

Power

Supply

Description

Main clock input

XIN

VCC1

I/O pins for the main clock oscillation circuit. Connect

a ceramic resonator or crystal oscillator between XIN

and XOUT(1). To apply an external clock, connect it to

XIN and leave XOUT open.

Main clock output

XOUT

VCC1

Sub clock input

XCIN

VCC1

I/O pins for a sub clock oscillation circuit. Connect a

crystal oscillator between XCIN and XCOUT (1).

To apply an external clock, connect it to XCIN and

leave XCOUT open

Sub clock output

XCOUT

VCC1

BCLK output

BCLK

VCC2

Output pin for BCLK signal

Clock output

CLKOUT

VCC2

This pin outputs the clock having the same frequency

as fC, f8, or f32

INT interrupt input

INT0 to INT2

VCC1

Low active input pins for

INT interrupt

INT3 to INT7

VCC2

NMI interrupt input

NMI

VCC1

Low active input pin for

NMI interrupt

Key input

interrupt input

KI0 to KI3

VCC1

Low active input pins for key input interrupt

Timer A

TA0OUT to

TA4OUT

I/O

VCC1

Timer A0 to A4 I/O pins (TA0OUT as an output pin is

N-channel open drain output)

TA0IN to TA4IN

VCC1

Timer A0 to A4 input pins

VCC1

Input pin for Z-phase

Timer B

TB0IN to TB5IN

VCC1

Timer B0 to B5 input pins

Three-phase motor

control timer

U, V, V, W, W

VCC1

Output pins for three-phase motor control timer output

VCC1

Input pin for three-phase motor control timer input

Serial interface

UART0 to UART2,

UART5 to UART7

CTS0 to CTS2,

CTS5

VCC1

Input pins to control data transmission

CTS6, CTS7

VCC2

RTS0 to RTS2,

RTS5

VCC1

Output pins to control data reception

RTS6, RTS7

VCC2

CLK0 to CLK2, CLK5

I/O

VCC1

Transfer clock I/O pins

CLK6, CLK7

I/O

VCC2

RXD0 to RXD2

, RXD5

VCC1

Serial data input pins

RXD6, RXD7

VCC2

TXD0 to TXD2

, TXD5

VCC1

Serial data output pins(2)

TXD6, TXD7

VCC2

CLKS1

VCC1

Output pin for transfer clock multiple-pin output func-

tion

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