R5F3640MNFB datasheet(65/398 Pages) RENESAS

65 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 44 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

6. Voltage Detection Circuit

Figure 6.8

Low Voltage Detection Interrupt Generation Circuit Operation Example

6.3

Limitations on Exiting Stop Mode

The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if

the CM10 bit in the CM1 register is set to 1 (stop mode) under the conditions below.

• the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled)

• the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled)

• the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit stop mode)

• the voltage applied to the VCC1 pin is higher than Vdet2 (the VC13 bit in the VCR1 register is 1)

If the microcomputer is set to enter stop mode when the voltage applied to the VCC1 pin drops below

Vdet2 and to exit stop mode when the voltage applied rises to Vdet2 or above, set the CM10 bit to 1 when

VC13 bit is 0 (VCC1 < Vdet2).

6.4

Limitations on Exiting Wait Mode

The low voltage detection interrupt is immediately generated and the microcomputer exits wait mode If

WAIT instruction is executed under the conditions below.

• the CM02 bit in the CM0 register is set to 1 (stop peripheral function clock)

• the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled)

• the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled)

• the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit wait mode)

• the voltage applied to the VCC1 pin is higher than Vdet2 (the VC13 bit in the VCR1 register is 1)

If the microcomputer is set to enter wait mode when the voltage applied to the VCC1 pin drops below

Vdet2 and to exit wait mode when the voltage applied rises to Vdet2 or above, perform WAIT instruc-

tion when the VC13 bit is 0 (VCC1 < Vdet2).

Output of the digital filter (2)

D42 bit

NOTES :

1. The D40 bit is set to 1 (low voltage detection interrupt enabled).

2. Output of the digital filter is shown in Figure 6.7.

Low voltage detection interrupt signal

No low voltage detection

interrupt signals are generated

when the D42 bit is “H.”

Sampling

Set the D42 bit to 0 (not

detected) by program.

VC13 bit

VCC1

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