R5F3640MNFB datasheet(79/398 Pages) RENESAS

79 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 58 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

8.2.6

RDY Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If input

on the

RDY pin is low at the last falling edge of BCLK of the bus cycle, one wait state is inserted in the

bus cycle. While in a wait state, the following signals retain the state in which they were when the

RDY

signal was acknowledged.

A0 to A19, D0 to D15,

CS0 to CS3, RD, WRL, WRH, WR, BHE, ALE, HLDA

Then, when the input on the

RDY pin is detected high at the falling edge of BCLK, the remaining bus

cycle is executed. Figure 8.4 shows Examples in which the Wait State was Inserted into Read Cycle by

RDY Signal. To use the RDY signal, set the corresponding bit (bits CS3W to CS0W) in the CSR regis-

ter to 0 (with wait state). When not using the

RDY signal, the RDY pin need to be pulled-up.

Figure 8.4

Examples in Which Wait State Was Inserted into Read Cycle by

RDY Signal

BCLK

CSi

(i = 0 to 3)

RDY

tsu (RDY-BCLK)

BCLK

CSi

(i = 0 to 3)

RDY

tsu (RDY-BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

tsu (RDY - BCLK)

: Wait using software

: Wait using RDY signal

: Duration for RDY input setup

Shown above is the case where bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register

are 00b (one wait state).

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