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R5F3640MNFB Datasheet(PDF) 29 Page - Renesas Technology Corp |
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R5F3640MNFB Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 398 page ![]() REJ09B0392-0064 Rev.0.64 Oct 12, 2007 Page 8 of 373 M16C/64 Group 1. Overview Under development Preliminary Specification Specification in this preliminary version is subject to change. Figure 1.5 Pin Assignment (Top View) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P0_0/AN0_0/D0 P0_1/AN0_1/D1 P0_2/AN0_2/D2 P0_3/AN0_3/D3 P0_4/AN0_4/D4 P0_5/AN0_5/D5 P0_6/AN0_6/D6 P0_7/AN0_7/D7 P1_0/CTS6/RTS6/D8 P1_1/CLK6/D9 P1_2/RXD6/SCL6/D10 VREF AVSS AVCC P10_0/AN0 P10_1/AN1 P10_2/AN2 P10_3/AN3 P9_5/ANEX0/CLK4 P9_6/ANEX1/SOUT4 P9_7/ADTRG/SIN4 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 M16C/64 Group PLQP0100KB-A (100P6Q-A) (top view) P4_2/A18 P4_3/A19 P5_6/ALE P5_5/HOLD P5_4/HLDA P5_3/BCLK P5_2/RD P5_7/RDY/CLKOUT P6_3/TXD0/SDA0 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P6_1/CLK0 P6_2/RXD0/SCL0 P6_0/CTS0/RTS0 P6_4/CTS1/RTS1/CTS0/CLKS1 P5_0/WRL/WR P5_1/WRH/BHE P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN(1) P7_0/TXD2/SDA2/TA0OUT(1) P4_5/CLK7/CS1 P4_6/RXD7/SCL7/CS2 P4_7/TXD7/SDA7/CS3 P4_4/CTS7/RTS7/CS0 NOTES: 1. N-channel open-drain output. 2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions. 3. Symbols in brackets [ ] represent a functional signal as a whole. VCC1 ports VCC2 ports (3) |
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