R5F3640MNFB datasheet(64/398 Pages) RENESAS

64 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 43 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

6. Voltage Detection Circuit

- indicates either 0 or 1 is settable.

NOTE:

The status except wait mode and stop mode is handled as normal mode. (Refer to 10. “Clock Gen-

eration Circuit”

)

Refer to 6.3 “Limitations on Exiting Stop Mode” and 6.4 “Limitations on Exiting Wait Mode”.

An interrupt request for voltage reduction is generated after the value of the VC13 bit changes and a

sampling time elapses. See Figure 6.8 “Low Voltage Detection Interrupt Generation Circuit

Operation Example”

for details.

Figure 6.7

Low Voltage detection Interrupt Generation Block Diagram

Table 6.2

Low Voltage Detection Interrupt Request Generation Conditions

Operating Mode

VC27 Bit

D40 Bit

D41 Bit

D42 Bit

CM02 Bit

VC13 Bit

Normal Operating Mode (1)

0 to 1

0 to 1 (3)

1 to 0 (3)

Wait Mode (2)

0 to 1

0 to 1 (3)

1 to 0 (3)

0 to 1

Stop Mode (2)

0 to 1

Table 6.3

Sampling Periods

CPU Clock

(D4INT clock)

(MHz)

Sampling Clock (

μs)

DF1 to DF0 = 00

(CPU clock divided by 8)

DF1 to DF0 = 01

(CPU clock divided by 16)

DF1 to DF0 = 10

(CPU clock divided by 32)

DF1 to DF0 = 11

(CPU clock divided by 64)

3.0

6.0

12.0

24.0

Low voltage detection interrupt generation circuit

Watchdog timer

interrupt signal

The D42 bit is set to 0 (not

detected) by program. When the

VC27 bit is set to 0 (low voltage

detection circuit disabled), the

D42 bit is set to 0.

VC27

VC13

Low voltage detection circuit

D4INT clock

(the clock with

which it operates

also in wait mode)

D42

DF1, DF0

1/2

00b

01b

10b

11b

1/2

1/8

Non-maskable

interrupt sognal

Oscillation stop,

re-oscillation

detection interrupt

signal

Low voltage

detection

interrupt signal

Watchdog timer block

This bit is set to 0 (not detected) by program.

Watchdog timer

underflow signal

D43

D41

CM02

WAIT instruction (wait mode)

D40

VCC1

VREF

Noise

rejection

(Rejection range : 200 ns)

Low voltage

detection

signal

The low voltage detection

signal becomes “H” when the

VC27 bit is set to 0

(disabled).

Noise

rejection

circuit

Digital

filter

CM10

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