R5F3640MNFB datasheet(74/398 Pages) RENESAS

74 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 53 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

Bus

During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform

data input /output to and from external devices. These bus control pins include A0 to A19, D0 to D15,

CS0

CS3, RD, WRL /WR, WRH / BHE, ALE, RDY, HOLD, HLDA, and BCLK.

8.1

Bus Mode

Bus mode, either multiplexed or separate, can be selected using bits PM05 and PM04 in the PM0 regis-

ter. Table 8.1 shows the Difference between Separate Bus and Multiplexed Bus.

8.1.1

Separate Bus

In this bus mode, data and address are separate.

8.1.2

Multiplexed Bus

In this bus mode, data and address are multiplexed.

8.1.2.1

When the Input Level on BYTE Pin is High (8-Bit Data Bus)

D0 to D7 and A0 to A7 are multiplexed.

8.1.2.2

When the Input Level on BYTE Pin is Low (16-Bit Data Bus)

D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. Exter-

nal devices connecting to a multiplexed bus are allocated to only the even addresses of the micro-

computer. Odd addresses cannot be accessed.

NOTES:

See Table 8.6 “Pin Functions for Each Processor Mode” for bus control signals other than the

above.

It changes with a setting of PM05 and PM04, and area to access.

See Table 8.6 “Pin Functions for Each Processor Mode” for details.

Table 8.1

Difference between Separate Bus and Multiplexed Bus

Pin Name (1)

Separate Bus

Multiplexed Bus

BYTE = “H”

BYTE = “L”

P0_0 to P0_7 / D0 to D7

D0 to D7

(NOTE 2)

P1_0 to P1_7 / D8 to D15

D8 to D15

I/O port

P1_0 to P1_7

(NOTE 2)

P2_0 / A0 (/ D0 / -)

P2_1 to P2_7 / A1 to A7

(/ D1 to D7 / D0 to D6)

A1 to A7

A1 to A7 D1 to D7

A1 to A7 D0 to D6

P3_0 / A8 (/ - / D7)

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