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R5F3640MNFB Datasheet(PDF) 57 Page - Renesas Technology Corp |
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R5F3640MNFB Datasheet(HTML) 57 Page - Renesas Technology Corp |
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57 / 398 page  REJ09B0392-0064 Rev.0.64 Oct 12, 2007 Page 36 of 373 Under development Preliminary Specification Specification in this preliminary version is subject to change. M16C/64 Group 5. Reset 5.6 Internal Space Figure 5.3 shows CPU Register Status After Reset. Refer to 4. “Special Function Registers (SFRs)” for SFR states after reset. Figure 5.3 CPU Register Status After Reset b15 b0 Data register (R0) Address register (A0) Frame base register (FB) Program counter (PC) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) 0000h 0000h 0000h C D Z S B O I U IPL 0000h 0000h 0000h 0000h 0000h b19 b0 Content of addresses FFFFEh to FFFFCh b15 b0 b15 b0 b15 b0 b7 b8 00000h Data register (R1) Data register (R2) Data register (R3) Address register (A1) 0000h 0000h 0000h |
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