R5F3640MNFB datasheet(95/398 Pages) RENESAS

95 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 74 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

10. Clock Generation Circuit

10.1

Type of the Clock Generation Circuit

4 circuits are incorporated to generate the system clock signal:

• Main clock oscillation circuit

• Sub clock oscillation circuit

• 125 kHz on-chip oscillator

• PLL frequency synthesizer

Table 10.1 lists the Clock Generation Circuit Specifications. Figure 10.1 shows the System Clock Gener-

ation Circuit.

Figures 10.2 to 10.6 show the clock-related registers.

NOTE:

The PLL frequency synthesizer uses the main clock oscillation circuit as a reference clock source.

The items above are based on those of the main clock oscillation circuit.

Table 10.1

Clock Generation Circuit Specifications

Item

Main Clock

Oscillation Circuit

Sub Clock

Oscillation Circuit

125 kHz On-Chip

Oscillator

PLL Frequency

Synthesizer

Use of Clock

CPU clock source

Peripheral function

clock source

CPU clock source

Clock source of

timer A and B.

CPU clock source

Peripheral function

clock source

CPU and peripheral

function clock

sources when the

main clock stops

oscillating

CPU clock source

Peripheral function

clock source

Clock Frequency

0 to 20 MHz

32.768 kHz

About 125 kHz

10 to 25 MHz

Usable Oscillator

Ceramic oscillator

Crystal oscillator

- (1)

Pins to Connect

Oscillator

XIN, XOUT

XCIN, XCOUT

- (1)

Oscillation Stop,

Restart Function

Presence

Oscillator Status

After Reset

Oscillating

Stopped

Oscillating

Stopped

Other

Externally derived clock can be input

- (1)

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