R5F3640MNFB datasheet(84/398 Pages) RENESAS

84 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 63 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

NOTES:

To use the

RDY signal, set the CSiW bit to 0 (with wait state).

To access in multiplexed bus mode, set the CSiW bit to 0 (with wait state).

When the PM17 bit is set to 1 and accesses an external area, set the CSiW bit to 0 (with wait state).

After reset, the PM17 bit is set to 0 (without wait state), bits CS0W to CS3W are set to 0 (with wait

state), and the CSE register is set to 00h (one wait state for

CS0 to CS3). Therefore, all external

areas are accessed with one wait state.

Table 8.9

Bits and Bus Cycles Related to Software Wait (External Area)

Area

Bus Mode

Setting of Software-Wait-related Bits

Software

Wait

Bus Cycle

PM1 Regis-

ter PM17 Bit

CSR Register

CSiW Bit (1)

CSE Register

Bits CSEi1W to

CSEi0W

External

Area

Separate

Bus

00b

No wait

1 BCLK cycle

(Read)

2 BCLK cycles

(Write)

-0

00b

1 wait

2 BCLK cycles (4)

01b

2 waits

3 BCLK cycles

10b

3 waits

4 BCLK cycles

0 (3)

00b

1 wait

2 BCLK cycles

Multiplexed

Bus

0 (2)

00b

1 wait

3 BCLK cycles

0 (2)

01b

2 waits

3 BCLK cycles

0 (2)

10b

3 waits

4 BCLK cycles

0 (2, 3)

00b

1 wait

3 BCLK cycles

i = 0 to 3

− indicates that either 0 or 1 can be set.

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