R5F3640MNFB datasheet(91/398 Pages) RENESAS

91 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 70 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

9. Memory Space Expansion Function

Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode.

In this example, the

CS pin of 4-Mbyte ROM is connected to the CS0 pin of the microcomputer. The 4-

Mbyte ROM address input pins AD21, AD20, and AD19 are connected to pins

CS3, CS2, and CS1 of

the microcomputer, respectively. The address input AD18 pin is connected to the A19 pin of microcom-

puter. Figures 9.7 to 9.9 show the relationship of addresses between the 4-Mbyte ROM and the micro-

computer for the case of a connection example in Figure 9.6.

In microprocessor mode or in memory expansion mode where the PM13 bit in the PM1 register is 0,

banks are located every 512 Kbytes. Setting the OFS bit in the DBR register to 1 (offset) allows the

accessed address to be offset by 40000h, so that even the data overlapping at a bank boundary can be

accessed in succession.

In memory expansion mode where the PM13 bit is 1, each 512-Kbyte bank can be accessed in 256

Kbyte units by switching them over with the OFS bit.

Because the SRAM can be accessed on condition that the chip select signals S2 = “H” and

S1 = “L”,

CS0 and CS2 can be connected to S2 and S1, respectively. If the SRAM does not have the input pins

which accept “H” active and “L” active chip select signals (

S1, S2), CS0 and CS2 should be decoded

external to the chip.

Figure 9.6

External Memory Connect Example in 4-Mbyte Mode

D0 to D7

A0 to A16

A17

CS1

CS2

CS3

CS0

A19

DQ0 to DQ7

AD0 to AD16

AD17

AD18

AD19

DQ0 to

DQ7

AD0 to

AD16

AD20

AD21

NOTE :

1. If only one chip select pin (S1 or S2) is present, using an external circuit is required for decode.

(1)

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