R5F3640MNFB datasheet(76/398 Pages) RENESAS

76 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 55 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

Figure 8.1

CSR Register

b7 b6 b5 b4

Chip Select Control Register

Symbol

CSR

Address

0008h

Bit Symbol

Bit Name

After Reset

01h

1. When the RDY signal is used in the area indicated by CSi (i = 0 to 3) or the multiplex bus is used, set the CSiW bit to 0

(wait state).

2. When the PM17 bit in the PM1 register is set to 1 (wait state), set the CSiW bit to 0 (wait state).

3. When the CSiW bit = 0 (wait state), the number of wait states can be selected using bits CSEi1W to CSEi0W in the CSE

Function

CS0

0 : Disable chip select output

(functions as I/O port)

1 : Enable chip select output

CS0 output enable bit

CS1

CS1 output enable bit

CS2

CS2 output enable bit

CS3

CS3 output enable bit

CS0W

0 : Wait state

1 : No wait state (1, 2, 3)

CS0 wait bit

CS1W

CS1 wait bit

CS2W

CS2 wait bit

CS3W

CS3 wait bit

NOTES :

R5F3640MNFB Datasheet(PDF) 76 Page - Renesas Technology Corp

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