R5F3640MNFB datasheet(98/398 Pages) RENESAS

98 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 77 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

10. Clock Generation Circuit

Figure 10.3

CM1 Register

b6 b5 b4

System Clock Control Register 1 (1)

Symbol

CM1

Address

0007h

Bit Symbol

Bit Name

CM10

After Reset

00100000b

NOTES :

1. Rewrite this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. When entering stop mode or the CM05 bit is set to 1 (main clock stops) in low speed mode, the CM15 bit is set to

1 (drive capacity high).

3. This bit is valid when the CM06 bit is set to 0 (bits CM16 and CM17 enabled).

4. If the CM10 bit is set to 1 (stop mode), XOUT is held “H” and the internal feedback resistor is disconnected. Pins

XCIN and XCOUT are in high-impedance state. When the CM11 bit is set to 1 (PLL clock), or the CM20 bit in the

CM2 register is set to 1 (oscillation stop detection function enabled), do not set the CM10 bit to 1.

5. After setting the PLC07 bit in the PLC0 register to 1 (PLL operation), wait tsu (PLL) elapses before setting the

CM11 bit to 1 (PLL clock).

6. When the PM21 bit in the PM2 register is set to 1 (disable clock modification), this bit remains unchanged even if

writing to bits CM10 and CM11. When the CSPRO bit in the CSPR register is set to 1 (count source protection

mode), this bit remains unchanged even if writing to the CM10 bit.

7. The CM11 bit is valid when bits CM07 and CM21 are set to 0.

8. The CM14 bit can be set to 1 (125 kHz on-chip oscillator off) when the CM21 bit is set to 0 (main clock or PLL

clock). When the CM21 bit is set to 1 (125 kHz on-chip oscillator clock), the CM14 bit is set to 0 (125 kHz on-chip

oscillator on) and remains unchanged even if writing 1 to this bit.

9. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode), the CM14 bit is automatically

set to 0 (125 kHz on-chip oscillator on) and remains unchanged even if writing a 1 to this bit (125 kHz on-chip

oscillator does not stop).

Function

All clock stop control bit (4, 6)

—

(b3-b2)

CM14

Reserved bits

0 : Clock on

1 : All clocks off (stop mode)

CM15

Set to 0

CM16

0 : 125 kHz on-chip oscillator on

1 : 125 kHz on-chip oscillator off

0 : Low

1 : High

125 kHz on-chip oscillator stop

bit (8, 9)

XIN-XOUT drive capacity

select bit (2)

CM11

System clock select bit 1 (6, 7)

0 : Main clock

1 : PLL clock (5)

CM17

Main clock division select bit 1

(3)

b7 b6

0 0 : No division mode

0 1 : Divide-by-2 mode

1 0 : Divide-by-4 mode

1 1 : Divide-by-16 mode

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