R5F3640MNFB datasheet(101/398 Pages) RENESAS

101 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 80 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

10. Clock Generation Circuit

Figure 10.6

PLC0 Register

b7 b6 b5 b4

PLL Control Register 0 (1, 2)

Symbol

PLC0

Address

001Ch

Bit Symbol

Bit Name

After Reset

0X01X010b

NOTES :

1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enabled).

2. When the PM21 bit in the PM2 register is 1 (clock modification disabled), writing to this register has no

effect.

3. Bits PLC00 to PLC02, PLC04, and PLC5 can only be modified when the PLC07 bit = 0 (PLL turned off). The

value once written to this bit cannot be modified.

4. Before setting the PLC07 bit to 1, set the CM05 bit to 0 (main clock oscillation).

Function

—

(b3)

PLC04

PLC05

—

(b6)

PLC07

No register bit. If necessary, set to 0. Read as undefined value

0 : PLL off

1 : PLL on

Operation enable bit (4)

Reserved bit

Read as undefined value

Reference frequency counter

set bit (3)

b5 b4

0 0 : No division

0 1 : Divide-by-2

1 0 : Divide-by-4

1 1 : Do not set

PLC00

PLL multiplying factor

select bit (3)

PLC01

PLC02

b2 b1 b0

0 0 0 : Do not set

0 0 1 : Multiply by 2

0 1 0 : Multiply by 4

0 1 1 : Multiply by 6

1 0 0 : Multiply by 8

1 0 1 :

1 1 0 :

Do not set

1 1 1 :

—

R5F3640MNFB Datasheet(PDF) 101 Page - Renesas Technology Corp

R5F3640MNFB Datasheet(HTML) 101 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL