R5F3640MNFB datasheet(56/398 Pages) RENESAS

56 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 35 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

5. Reset

5.2

Brown-out Reset

The microcomputer resets pins, the CPU, or SFRs by setting the built-in voltage detection 0 circuit. The

voltage detection 0 circuit monitors the voltage applied to the VCC1 pin (Vdet0).

The microcomputer resets pins, the CPU, and SFR as soon as the voltage that is applied to the VCC1 pin

drops to Vdet0 or below.

Then, 125 kHz on-chip oscillator clock starts counting when the voltage that is applied to the VCC1 pin

goes up to Vdet0 or above. The internal reset signal becomes “H” after the 125 kHz on-chip oscillator

clock is counted 32 times, and then reset sequence starts (see Figure 5.2). The 125 kHz on-chip oscillator

clock divided by 8 is automatically selected as a CPU clock after reset.

Refer to 4. “Special Function Registers (SFRs)” for the SFR status after brown-out reset.

The internal RAM is not reset. When the voltage that is applied to the VCC1 pin drops to Vdet0 or below

while writing data to the internal RAM, the internal RAM is in an indeterminate state.

Refer to 6. “Voltage Detection Circuit” for details of the voltage detection 0 circuit.

5.3

Software Reset

The microcomputer resets pins, the CPU, and SFRs when the PM03 bit in the PM0 register is set to 1

(microcomputer reset). Then the microcomputer executes the program in an address determined by the

reset vector. The 125 kHz on-chip oscillator clock divided by 8 is automatically selected as a CPU clock

after reset.

In the software reset, the microcomputer does not reset a part of the SFRs. Refer to 4. “Special Func-

tion Registers (SFRs)”

for details.

The internal RAM is not reset.

5.4

Watchdog Timer Reset

The microcomputer resets pins, the CPU, and SFRs when the PM12 bit in the PM1 register is set to 1

(reset when watchdog timer underflows) and the watchdog timer underflows. Then the microcomputer

executes the program in an address determined by the reset vector. The 125 kHz on-chip oscillator clock

divided by 8 is automatically selected as a CPU clock after reset.

In the watchdog timer reset, the microcomputer does not reset a part of the SFRs. Refer to 4. “Special

Function Registers (SFRs)”

for details.

The internal RAM is not reset. When the watchdog timer underflows while writing data to the internal

RAM, the internal RAM is in an indeterminate state.

Refer to 13. “Watchdog Timer” for details.

5.5

Oscillation Stop Detection Reset

The microcomputer resets and stops pins, the CPU, and SFRs when the CM27 bit in the CM2 register is

0 (reset when oscillation stop detected), if it detects main clock oscillation circuit stop. Refer to 10.6

“Oscillation Stop and Re-Oscillation Detect Function”

for details.

In the oscillation stop detection reset, the microcomputer does not reset a part of the SFRs. Refer to 4.

“Special Function Registers (SFRs)”

for details. Processor mode remains unchanged since bits PM01

to PM00 in the PM0 register are not reset.

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