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R5F3640MNFB Datasheet(PDF) 27 Page - Renesas Technology Corp |
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R5F3640MNFB Datasheet(HTML) 27 Page - Renesas Technology Corp |
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27 / 398 page ![]() REJ09B0392-0064 Rev.0.64 Oct 12, 2007 Page 6 of 373 M16C/64 Group 1. Overview Under development Preliminary Specification Specification in this preliminary version is subject to change. 1.4 Block Diagram Figure 1.3 is a M16C/64 Group Block Diagram. Figure 1.3 Block Diagram Clock synchronous serial I/O (8 bits × 2 channels) DMAC (4 channels) Internal peripheral functions Clock generation circuits XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator (125 kHz) NOTES : 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Port P0 8 Port P1 8 Port P2 8 8 8 8 Port P5 Port P4 Port P3 UART or clock synchronous serial I/O (6 channels) VCC2 ports R0L R0H R1H R1L R2 R3 A0 A1 FB SB ISP USP INTB FLG M16C/60 Series CPU core Memory ROM (1) RAM (2) Multiplier PC Watchdog timer (15 bits) A/D converter (10 bits × 26 channels) CRC calculation circuit (CCITT) (Polynomial X16 + X12 + X5 + 1) D/A converter (8 bits × 2 channels) Three-phase motor control circuit 8 8 8 Port P7 Port P8 Port P9 Port P10 8 Port P6 8 Timer (16-bit) Outputs (Timer A): 5 Inputs (Timer B): 6 VCC1 ports |
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