R5F3640MNFB datasheet(23/398 Pages) RENESAS

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REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 2 of 373

M16C/64 Group

1. Overview

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

1.2

Specifications

Tables 1.1 and 1.2 list Specifications Outline.

NOTE:

IEBus is a registered trademark of NEC Electronics Corporation.

Table 1.1

Specifications (1)

Item

Function

Specification

CPU

Central processing unit

M16C/60 core (multiplier: 16-bit × 16-bit ! 32 bits,

multiply and accumulate instruction: 16 × 16 + 32 !32 bits)

• Number of basic instructions: 91

• Minimum instruction execution time:

40.0 ns ( f(BCLK) = 25 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)

• Operating modes: Single-chip, memory expansion, and microproces-

sor

Memory

ROM, RAM,

data flash

See Table 1.3 Product List.

Voltage

Detection

Voltage detection circuit

Low-voltage detection unit

Clock

Clock generation circuit

• 4 circuits: Main clock, sub clock, on-chip oscillator (125 kHz), PLL

• Oscillation stop detection: Main clock oscillation stop detection and re-

oscillation detection function

• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8 and 16

• Low-power consumption modes: Wait mode, stop mode

External Bus

Expansion

Bus and memory expansion

• Address space: 1 Mbyte

• External bus interface: 0 to 3 waits states, chip select 4 outputs, mem-

ory area expansion function (up to 4 Mbytes), 3 V, 5 V interface

• Bus format: Separate bus or multiplexed bus selectable, data bus

width selectable (8 or 16 bits), number of address buses selectable

(12, 16, or 20 buses)

I/O Ports

Programmable I/O ports

• CMOS I/O ports: 85, selectable pull-up resistor

• Nch open drain ports: 3

Interrupts

• Interrupt vectors: 70

• External interrupt input: 13 (

NMI, INT × 8, key input × 4)

• Interrupt priority levels: 7

Watchdog Timer

15 bits × 1 (with prescaler)

Automatic reset start function selectable

DMA

DMAC

• 4 channels, cycle steal mode

• Trigger sources: 43

• Transfer modes: 2 (single transfer, repeat transfer)

Timer

Timer A

16-bit timer × 5

Timer mode, event counter mode, one shot timer mode, pulse width

modulation (PWM) mode

Event counter two-phase pulse signal processing (two-phase encoder

input) × 3 channels

Timer B

16-bit timer × 6

Timer mode, event counter mode, pulse period measurement mode,

pulse width measurement mode

Timer functions for three-

phase motor control

Three-phase inverter control (timer A1, timer A2, timer A4, timer B2),

On-chip dead time timer

Serial Inter-

face

UART0 to UART2, UART5 to

UART7

Clock synchronous/asynchronous × 6 channels

I2C-bus, IEBus (1), special mode 2, SIM (UART2)

SI/O3, SI/O4

Clock synchronization only × 2 channels

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