R5F3640MNFB datasheet(80/398 Pages) RENESAS

80 / 398 page

REJ09B0392-0064 Rev.0.64

Oct 12, 2007

Page 59 of 373

Under development

Preliminary Specification

Specification in this preliminary version is subject to change.

M16C/64 Group

8. Bus

8.2.7

HOLD Signal

This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the

input on the

HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access at

that time finishes. The microcomputer remains in the hold state while the

HOLD pin is held low, during

which time the

HLDA pin outputs a low-level signal.

Table 8.5 shows the Microcomputer Status in Hold State.

Bus-using priorities are given to

HOLD, DMAC, and CPU in descending order. However, if the CPU is

accessing an odd address in word units, the DMAC cannot gain control of the bus during two separate

accesses.

Figure 8.5

Bus-Using Priorities

NOTES:

When I/O port function is selected.

The watchdog timer does not stop when the CSPRO bit in the CSPR register is set to 1 (count source

protection mode enabled).

8.2.8

BCLK Output

If the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency as that

of the CPU clock is output as BCLK from the BCLK pin. Refer to 10.2 “CPU Clock and Peripheral

Function Clock”

Table 8.5

Microcomputer Status in Hold State

Item

Status

BCLK

Output

A0 to A19, D0 to D15,

CS0 to CS3, RD, WRL,WRH,

WR, BHE

High-impedance

I/O ports

P0, P1, P3, P4 (1)

High-impedance

P6 to P10

Maintains status when

HOLD signal is received

HLDA

Output “L”

Internal Peripheral Circuits

On (but watchdog timer stops) (2)

ALE

Undefined

HOLD > DMAC > CPU

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