MFS2301BMBACEP datasheet(30/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.8 MCU programming

MCU programming can be done at any time. When the watchdog functionality is enabled by OTP

(WD_INF_OTP = 0), NXP recommends extending the watchdog period (up to 1024 ms) or to set it as infinite

(window is fully opened) during INIT phase. This will prevent any watchdog error detection and RSTB pin

assertion while programming. If the watchdog is not “disabled” (window set as infinite), the user will have to

refresh it during the MCU programming.

The advised procedure to change the watchdog period to infinite is the following:

1. Make sure the FS23 is in Normal mode by reading M_STATUS register.

2. Send a GO2INIT request by writing in M_SYS_CFG register.

3. Make sure the FS23 is in INIT mode by reading M_STATUS register.

4. Set the infinite watchdog period by writing 4b’0000 in the WDW_PERIOD and WDW_RECOVERY fields in

FS_WDW register.

5. Exit INIT mode by clearing the LOCK_INIT bit, then sending a good WD refresh.

12.9 Best of supply

12.9.1 Functional description

The VBOS regulator manages the best of supply from VSUP or V1 (in case V1 is an HVBUCK) to efficiently

generate the internal biasing of the device, in every Device mode. VBOS is also the supply of V1 high-side and

low-side gate drivers in HVBUCK use case.

VBOS undervoltage may not guarantee the full functionality of the device. Consequently, VBOS_UV detection

powers down the device by going into Fail-safe state.

VBOS is composed of two regulators implemented in parallel: VBOS_HP used to supply the HP analog internal

biasing, and VBOS_LP used to supply the internal biasing in Low-Power modes.

At power up, VBOS_LP is automatically enabled, and VBOS_HP is enabled later when the HP analog circuitry

is enabled. At power up, both VBOS_LP and VBOS_HP are generated from VSUP.

In HVBUCK use case only:

• In Normal mode, VBOS can be connected to V1 if V1 = 5 V (configurable by OTP + SPI/I2C, using

VBOS2V1_SW_ALWAYS_EN bit). In this case, VBOS will stay connected to V1 in LPON mode.

• In LPON mode, VBOS can be connected to V1 using VBOS2V1_SW_LP_EN _OTP bit. This feature allows

the user to optimize the efficiency, as the current consumption benefits from the VBAT to V1 ratio.

• When waking-up from LPON mode, VBOS will stay connected to V1 if VBOS2V1_SW_ALWAYS_EN = 1.

In HVLDO1 use case, VBOS is always supplied from VSUP.

In LPOFF mode, only VBOS_LP is enabled.

The behavior of VBOS regulator is summarized in Figure 18.

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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