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MFS2301BMBACEP Datasheet(PDF) 77 Page - NXP Semiconductors |
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MFS2301BMBACEP Datasheet(HTML) 77 Page - NXP Semiconductors |
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77 / 230 page  NXP Semiconductors FS23 Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers 19 Safety 19.1 Functional description The FS23 includes multiple safety mechanisms to guarantee the functional safety of the system, and reach up to ASIL B level. Safety features are configurable, either by OTP or by SPI/I2C, allowing scalability depending on the application needs. The FS23 also provides an on-demand ABIST to cover latent faults. aaa-051464 Reset driver LIMP0 driver OTP ABIST Watchdog V0MON V1MON V3MON Safety features RSTB VMON_EXT FCCU1 LIMP0 Digital state machine Voltage supervision MCU failure monitoring (FCCU) V2MON FCCU2 Fail-safe output driver FS0B Figure 43. Fail-safe features block diagram 19.2 Watchdog The FS23 provides a watchdog monitoring, as a software monitoring of the MCU. The watchdog functionality can be disabled by OTP using WD_INF_OTP bit. When WD_INF_OTP bit is equal to 1, the watchdog period is always considered as infinite. There is no need to refresh the watchdog, except to release the safety pins. In LPON mode, the watchdog stays enabled or is disabled depending on WD_DIS_LPON bit (configurable during INIT phase). When enabled in LPON, the watchdog operates in Timeout mode. The watchdog uses two keys, 0x5AB2 (default value after POR) and 0xD564, to validate the answer. The key is stored in the WD_TOKEN register, and is changed alternatively after each good WD refresh. The MCU reads the WD_TOKEN register and writes the correct answer (WD_TOKEN register value) through the SPI/I2C in WD_ANSWER register, in the right timing. The WD error counter is incremented when the answer is wrong or not given at the right moment, or not given at all at the end of the watchdog period. The first good watchdog refresh closes the INIT phase if LOCK_INIT = 0. The first good watchdog refresh is sent by the MCU in less than 256 ms (default period duration). Then the watchdog window is running and the MCU must refresh the watchdog every period. The duration of the watchdog period is configurable from 1 ms to 1024 ms during operation using WDW_PERIOD[3:0] bits. The new watchdog window is effective after the next good watchdog refresh. The watchdog window can be disabled (during INIT phase only) by setting the WDW_PERIOD[3:0] to 4b’0000. The watchdog disable is effective when the INIT phase is closed. When a reset event is detected (an external event or one generated by the FS23 device), the watchdog is reset and the watchdog period is set to the default value. The period should be configured again when the MCU recovers from the reset. FS23 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 7.0 — 16 October 2024 Document feedback 77 / 230 |
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