MFS2301BMBACEP datasheet(53/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

15.3.1 LVIO3, LVIO4, LVI5 used as input

The LVIO3, LVIO4, and LVI5 pins can be used as simple wake-capable digital inputs. In this case, when the

device is in Normal mode, any event on the LVIO3, LVIO4, or LVI5 pins generates a flag (LVIOx_I), when not

masked (LVIOx_M). In Low-power ON mode, wake-up events are generated on level (high or low), depending

on LVIOx_WUCFG bits.

When used as a wake-up source, internal pulldown and pullup resistors can be enabled or disabled as per

LVIOxPUPD_OTP[1:0] bits.

The LVIO3, LVIO4, or LVI5 pins can also be configured as FCCU2 input, to provide MCU or external device

error detection in combination or independently of FCCU1 pin. This mechanism is detailed in Section 19.3.

When the SPI communication interface is used, the MOSI/LVI5 pin, is used a MOSI function. See Section 20.2.

15.3.2 LVIO3, LVIO4, LVO6 used as output

The LVIO3 and LVIO4 pins can be configured as digital outputs by OTP via LVIOx_XX_EN_OTP bits. The

LVIO3 and LVIO4 pins can then be used as high-side driver, low-side driver, push-pull driver or in 3-state,

depending on LVIOx_HS_EN_OTP and LVIOx_LS_EN_OTP bits. The LVIO3 and LVIO4 pins' output states can

be controlled by SPI/I2C using LVIOxHI and LVIOxLO control bits.

The LVIO3 and LVIO4 default output states can be configured by OTP using LVIOx_OUT_DFLT_OTP. They

can also be assigned to one of the power sequence slots (SLOT_0/1/2) by OTP using LVIOx_SLOT_OTP. In

this case, during power up, the pin follows the default state as soon as the OTP configuration is loaded in the

mirror registers and the pin state is inverted when the configured slot starts. At power down, the pin goes back

to its default value when the configured slot starts. See Figure 30 as an example of LVIO pins configuration, with

LVIO3 default state low and assigned to SLOT_1, and LVIO4 default state high assigned to SLOT_2.

aaa-051452

VBAT

LVIO3

(default 0)

LVIO4

(default 1)

OTP

Loaded

Slot 0

Tslot

Slot 1

Slot 2

Vsup > Vsup_UV

Figure 30. Example of LVIO pins configuration in the slots, at power-up.

The LVIO3 and LVIO4 pins can also be configured respectively as LIMP1 and LIMP2 pseudo-safety outputs, for

a local use case. These functions come in addition to the LIMP0 safety output pin, and are described in detail in

Section 19.6.6.

LVO6 can be used as push-pull driver, with 3-state default condition, when the I2C communication interface is

used. In this case, it can be controlled by I2C using LVO6HI and LVO6LO bits.

When SPI communication interface is used, MOSI/LVO6 pin is used as MISO function. See Section 20.2.

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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