MFS2301BMBACEP datasheet(98/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

• FS_I_WD_CFG[14:7]

The calculation to apply on the result of the concatenation is the same as the SPI/I2C CRC, using

x^8+x^4+x^3+x^2+1 polynomial. The MCU must write the obtained CRC in the FS_CRC register before closing

the INIT phase, after the modification of the INIT registers.

Once the INIT phase closes and the device is in Normal mode, the periodic CRC check is launched

automatically each 5 ms (TCRC) (<FTTI).

Each 5 ms, the device logic recalculates the CRC and compares it to the value stored in FS_CRC register. If

a mismatch is reported, the INIT_CRC_NOK_I bit is set and the safety outputs FS0B or LIMP0 are asserted

depending on their impact configuration (INIT_CRC_FS0B_IMPACT and INIT_CRC_LIMP0_IMPACT).

TA = −40 °C to 125 °C, unless otherwise specified. VSUP = 5.5 V to 40 V, unless otherwise specified. All voltages

referenced to ground.

Symbol

Parameter

Min

Typ

Max

Unit

Cyclic CRC check

TCRC

CRC check timing interval

5.5

TCRC_RUN

CRC maximum computation time

µs

Table 61. Cyclic CRC check characteristics

19.9 Clock monitoring

The 1 MHz is monitored for stuck-at faults in Normal mode. In case a stuck-at is detected, the three safety pins

— RSTB, FS0B, and LIMP0 — are asserted.

FS23

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Product data sheet

Rev. 7.0 — 16 October 2024

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MFS2301BMBACEP Datasheet(PDF) 98 Page - NXP Semiconductors