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MFS2301BMBACEP Datasheet(PDF) 102 Page - NXP Semiconductors

Part # MFS2301BMBACEP
Description  Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
PDF  230 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MFS2301BMBACEP Datasheet(HTML) 102 Page - NXP Semiconductors

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NXP Semiconductors
FS23
Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers
B31 B30 B29 B28 B27 B26 B25 B24 B23
B22
B21 B20 B19 B18 B17 B16
MOSI
Register address [6:0]
R/W
Write data [15:8]
MISO
General status flags
Register content before write
B15 B14 B13 B12 B11 B10 B09 B08 B07
B06
B05 B04 B03 B02 B01 B00
MOSI
Write data [7:0]
CRC [7:0]
MISO
Register content before write
CRC [7:0] - response
Table 67. SPI write command message construction
B31 B30 B29 B28 B27 B26 B25 B24 B23
B22
B21 B20 B19 B18 B17 B16
MOSI
Register address [6:0]
R/W
0x00
MISO
General status flags
Read data [15:8]
B15 B14 B13 B12 B11 B10 B09 B08 B07
B06
B05 B04 B03 B02 B01 B00
MOSI
0x00
CRC [7:0]
MISO
Read data [7:0]
CRC [7:0] - response
Table 68. SPI read command message construction
20.2.2 SPI status bits
Bit
Symbol
Description
Interrupt notification from M_HSx_FLG or M_CS_FLG_MSK registers
0 No event reported in M_HSx_FLG or M_CS_FLG_MSK registers
1 An interrupt or flag is present in M_HSx_FLG or M_CS_FLG_MSK registers
Reset on power-on reset (POR), cleared when all individual bits are cleared
31
HSxG
Flags reported: HS1_OL_I, HS1_OC_I, HS12_TSD_I, HS2_OL_I, HS2_OC_I, HS3_OL_I,
HS3_OC_I, HS34_TSD_I, HS4_OL_I, HS4_OC_I, WAKE1_OL_I, WAKE2_OL_I, HVIO1_
OL_I, HVIO2_OL_I
Interrupt notification from FS_SAFETY_FLG register (safety related errors)
0 No event reported in FS_SAFETY_FLG register
1 Safety-related interrupt or flag present in FS_SAFETY_FLG register
Reset on power-on reset (POR), cleared when all individual bits are cleared
30
SAFETYG
Flags reported: WD_NOK_I, FCCU12_I, FCCU1_I, FCCU2_I, INIT_CRC_NOK_I
Interrupt notification from M_CAN or M_LIN registers
0 No event present reported in M_CAN or M_LIN registers
1 An interrupt or flag is present in M_CAN or M_LIN registers
Reset on power-on reset (POR), cleared when all individual bits are cleared
29
PHYG
Flags reported: CAN_TSD_I, CAN_TXD_TO_I, LIN_TSD_I, LIN_TXD_TO_I, LIN_SC_I
Table 69. MISO general device status bits descriptions
FS23
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 7.0 — 16 October 2024
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