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SN8F5708 Datasheet(PDF) 119 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 119 Page - SONiX Technology Company |
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119 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. OPA Datasheet Rev. 2.4 119 18.2 OPA Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OPM PW3CM1 PW3CM0 PW2CM1 PW2CM0 PW1CM1 PW1CM0 OP1EN OP0EN P3CON P3CON7 P3CON6 P3CON5 P3CON4 P3CON3 P3CON2 P3CON1 P3CON0 OPM Register (0x9B) Bit Field Type Initial Description 7..2 Refer to other chapter(s) 1 OP1EN R/W 0 OP-Amp 1 enable bit. 0: Disable. OP-Amp 1 disable, OP1O/OP1P/OP1N pins are GPIO mode. 1: Enable. OP-Amp 1 enables, OP1O/OP1P/OP1N pins are OP-Amp 1 input and output pins. 0 OP0EN R/W 0 OP-Amp 0 enable bit. 0: Disable. OP-Amp 0 disable, OP0O/OP0P/OP0N pins are GPIO mode. 1: Enable. OP-Amp 0 enables, OP0O/OP0P/OP0N pins are OP-Amp 0 input and output pins. P3CON Register (0x9F) Bit Field Type Initial Description 7..6 Refer to other chapter(s) 5..0 P3CON[5:0] R/W 0x00 P3 configuration control bit*. 0: P3 can be analog input pin (OP input pin) or digital GPIO pin. 1: P3 is pure analog input pin and can’t be a digital GPIO pin. * P3CON [7:0] will configure related Port3 pin as pure analog input pin to avoid current leakage. |
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