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71M6541D/F/G Datasheet(PDF) 107 Page - Maxim Integrated Products |
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71M6541D/F/G Datasheet(HTML) 107 Page - Maxim Integrated Products |
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107 / 166 page ![]() 71M6541D/F/G and 71M6542F/G Data Sheet Rev 5 107 Table 75 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Table 75: I/O RAM Map – Functional Order Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CE and ADC MUX5 2100 MUX_DIV[3:0] MUX10_SEL[3:0] MUX4 2101 MUX9_SEL[3:0] MUX8_SEL[3:0] MUX3 2102 MUX7_SEL[3:0] MUX6_SEL[3:0] MUX2 2103 MUX5_SEL[3:0] MUX4_SEL[3:0] MUX1 2104 MUX3_SEL[3:0] MUX2_SEL[3:0] MUX0 2105 MUX1_SEL[3:0] MUX0_SEL[3:0] CE6 2106 EQU[2:0] U CHOP_E[1:0] RTM_E CE_E CE5 2107 U U U SUM_SAMPS[12:8] CE4 2108 SUM_SAMPS[7:0] CE3 2109 U U CE_LCTN[5:0] CE2 210A PLS_MAXWIDTH[7:0] CE1 210B PLS_INTERVAL[7:0] CE0 210C R R DIFFB_E DIFFA_E RFLY_DIS FIR_LEN[1:0] PLS_INV RTM0 210D U U U U U U RTM0[9:8] RTM0 210E RTM0[7:0] RTM1 210F RTM1[7:0] RTM2 2110 RTM2[7:0] RTM3 2111 RTM3[7:0] CLOCK GENERATION CKGN 2200 U U ADC_DIV PLL_FAST RESET MPU_DIV[2:0] LCD/DIO VREF TRIM FUSES TRIMT 2309 TRIMT[7:0] LCD/DIO LCD0 2400 LCD_E LCD_MODE[2:0] LCD_ALLCOM LCD_Y LCD_CLK[1:0] LCD1 2401 LCD_VMODE[1:0] LCD_BLNKMAP23[5:0] LCD2 2402 LCD_BAT R LCD_BLNKMAP22[5:0] LCD_MAP6 2405 LCD_MAP[55:48] LCD_MAP5 2406 LCD_MAP[47:40] |
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