SN8F5708 datasheet(143/204 Pages) SONIX

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SN8F5708 Series

SPI

Datasheet Rev. 2.4

143

21 SPI

The SPI a serial communicate interface for data exchanging from one MCU to one MCU or other

hardware peripherals. It is a simple 8-bit interface without a major definition of protocol, packet or

control bits. The SPI transceiver includes three pins, clock (SCK), data input and data output (MISO/

MOSI) to send data between master and slaver terminals. An optional slave select pin (SSN) can be

enabled by register in slave mode. The SPI interface builds in 4-mode which are the clock idle

status and the clock phases.



Full-duplex, 3-wire synchronous data transfer.



Master (SCK is clock output) or Slave (SCK is clock input) operation.



Seven SPI Master baud rates.



Slave Clock rate up to fcpu/8.



8-bit data transmitted MSB first, LSB last.



Serial clock with programmable polarity and phase.



Master Mode fault error flag with MCU interrupt capability.



Write collision flag protection.

21.1

SPI Operation

The SPCON register can control SPI operating function, such as: transmit/receive, clock rate, data

transfer direction, SPI clock idle status and clock control phase and enable this circuit. This SPI

circuit will transmit or receive 8-bit data automatically by setting SPEN in SPCON register and write

or read SPDAT register.

CPOL bit is designed to control SPI clock idle status. CPHA bit is designed to control the clock edge

direction of data receive. CPOL and CPHA bits decide the SPI format. The SPI data transfer direction

is MSB bit to LSB bit.

The SPI supports 4-mode format controlled by CPOL and CPHA bits. The edge direction is “Data

Transfer Edge”. When setting rising edge that means to receive and transmit one bit data at SCK

rising edge, and data transition is at SCK falling edge. When setting falling edge, that means to

receive and transmit one bit data at SCK falling edge, and data transition is at SCK rising edge.

“CPHA” is the clock phase bit controls the phase of the clock on which data is sampled. When

CPHA=1, the SCK first edge is for data transition, and receive and transmit data is at SCK 2nd edge.

When CPHA=0, the 1st bit is fixed already, and the SCK first edge is to receive and transmit data.

The SPI data transfer timing as following figure:

SN8F5708 Datasheet(PDF) 143 Page - SONiX Technology Company

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