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SN8F5708 Datasheet(PDF) 147 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 147 Page - SONiX Technology Company |
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147 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. SPI Datasheet Rev. 2.4 147 SPCON Register (0xE2) Bit Field Type Initial Description 7,1,0 SM[2:0] R/W 000 SPI baud rate generator (master mode only) 000: fcpu/2 001: fcpu/4 010: fcpu/8 011: fcpu/16 100: fcpu/32 101: fcpu/64 110: fcpu/128 111: reserved 6 SPEN R/W 0 SPI communication function 0: Disable 1: Enable 5 SSDIS R/W 0 Slave select pin function (MSTR = 0, CPHA = 0 only) 0: Enable slave selection pin (SSN) function 1: Disable slave select pin (SSN) function 4 MSTR R/W 1 SPI mode 0: Slave mode 1: Master mode 3 CPOL R/W 0 SCK pin idle status 0: SCK idle low 1: SCK idle high 2 CPHA R/W 1 Clock phase of data latch control 0: Data latched by the first of clock edge 1: Data latched by the second of clock edge |
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